Yvain Thonnart - Citegraph

Author Info

Name	Affiliation	Papers
YVAIN THONNART	CEA-LETI, MINATEC, Grenoble, France	43
Collaborators	Citations	PageRank
180	349	32.39
Referers	Referees	References
880	844	341

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100880

Publications (43 rows)

Collaborators (100 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
PROWAVES: Proactive Runtime Wavelength Selection for Energy-Efficient Photonic NoCs	2	0.38	2021
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management	3	0.45	2021
SE2 - Going Remote - Challenges and Opportunities to Remote Learning, Work, and Collaboration.	0	0.34	2021
POPSTAR - a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems.	0	0.34	2020
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm<sup>2</sup> Inter-Chiplet Interconnects and 156mW/mm<sup>2</sup>@ 82%-Peak-Efficiency DC-DC Converters	0	0.34	2020
19.2 A 110mK 295µW 28nm FDSOI CMOS Quantum Integrated Circuit with a 2.8GHz Excitation and nA Current Sensing of an On-Chip Double Quantum Dot.	0	0.34	2020
WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs	0	0.34	2019
Latency Improvement of an Industrial SoC System Interconnect using an Asynchronous NoC Backbone	0	0.34	2019
A 10Gb/s Si-photonic transceiver with 150μW 120μs-lock-time digitally supervised analog microring wavelength stabilization for 1Tb/s/mm2 Die-to-Die Optical Networks.	0	0.34	2018
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.	2	0.47	2017
10 Gbps, 560 fJ/b TIA and modulator driver for optical networks-on-chip in CMOS 65nm	0	0.34	2016
8.1 a 4x4x2 homogeneous scalable 3d network-on-chip circuit with 326mflit/s 0.66pj/b robust and fault-tolerant asynchronous 3d links	10	0.78	2016
Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks.	6	0.53	2016
Efficiency Optimization of Silicon Photonic Links in 65-nm CMOS and 28-nm FDSOI Technology Nodes.	7	0.58	2016
Coherent crosstalk noise analyses in ring-based optical interconnects	7	0.51	2015
Complementary communication path for energy efficient on-chip optical interconnects	0	0.34	2015
Two-phase protocol converters for 3D asynchronous 1-of-n data links	3	0.49	2015
Fine-Grain Dvfs And Avfs Techniques For Complex Soc Design: An Overview Of Architectural Solutions Through Technology Nodes	0	0.34	2015
3D advanced integration technology for heterogeneous systems	4	0.56	2015
A Fine-Grain Variation-Aware Dynamic ${\rm Vdd}$-Hopping AVFS Architecture on a 32 nm GALS MPSoC.	0	0.34	2014
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding F MAX tracking	0	0.34	2014
Introduction to the special session on "Silicon photonic interconnects: an illusion or a realistic solution?".	0	0.34	2014
Technology assessment of silicon interposers for manycore SoCs: Active, passive, or optical?	3	0.39	2014
A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC	0	0.34	2013
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs	6	0.60	2013
An Iterative Computational Technique for Performance Evaluation of Networks-on-Chip	10	0.52	2013
A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits	20	1.08	2012
3D NoC using through silicon Via: An asynchronous implementation.	6	0.44	2011
A fully-asynchronous low-power framework for GALS NoC integration	60	6.51	2010
An analytical method for evaluating Network-on-Chip performance	19	0.70	2010
A 477mW NoC-based digital baseband for MIMO 4G SDR.	19	1.11	2010
Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC Platforms	0	0.34	2010
A Communication and configuration controller for NoC based reconfigurable data flow architecture	12	1.03	2009
An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application	22	1.45	2009
Power Reduction of Asynchronous Logic Circuits Using Activity Detection	8	1.04	2009
Design and Implementation of a GALS Adapter for ANoC Based Architectures	20	1.39	2009
An Asynchronous Power Aware and Adaptive NoC Based Circuit	51	2.21	2009
Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application	7	0.85	2009
Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction.	7	0.71	2008
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application	3	0.40	2008
Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip	2	0.43	2007
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip	20	0.98	2007
ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC	10	0.74	2007