Name
Abstract | ||
|---|---|---|
In an integrated CPU-GPU system, the CPU executes code that is profoundly different than in past CPU-only environments. This new code's characteristics should drive future CPU design and architecture. Post-GPU code has lower instruction-level parallelism, more difficult branch prediction, and loads and stores that are significantly harder to predict. Post-GPU code exhibits much smaller gains from the availability of multiple cores, owing to reduced thread-level parallelism. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/MM.2012.57 | IEEE Micro |
Keywords | Field | DocType |
difficult branch prediction,new code,integrated cpu-gpu system,instruction-level parallelism,cpu-gpu integration,reduced thread-level parallelism,multiple core,future cpu design,smaller gain,past cpu-only environment,post-gpu code,central processing unit,parallel processing,computational modeling,benchmark testing,hidden markov models | Central processing unit,Programming paradigm,Computer science,Efficient energy use,Parallel computing,Control flow,CPU modes,Graphics processing unit,CPU shielding,Benchmark (computing) | Journal |
Volume | Issue | ISSN |
32 | 6 | 0272-1732 |
Citations | PageRank | References |
9 | 0.50 | 11 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Manish Arora | 1 | 166 | 11.88 |
| Siddhartha Nath | 2 | 240 | 15.01 |
| Subhra Mazumdar | 3 | 28 | 3.45 |
| Scott B. Baden | 4 | 519 | 67.52 |
| Dean M. Tullsen | 5 | 4208 | 265.60 |