Name
Affiliation
Papers
SIDDHARTHA NATH
University of California, San Diego
21
Collaborators
Citations 
PageRank 
47
240
15.01
Referers 
Referees 
References 
651
682
246
Search Limit
100682
Title
Citations
PageRank
Year
Optimal Scheduling and Allocation for IC Design Management and Cost Reduction.20.372017
Learning-based prediction of embedded memory timing failures during initial floorplan design.80.572016
BEOL stack-aware routability prediction from placement using data mining techniques30.382016
Toward Metrics of Design Automation Research Impact30.392015
Optimization of Overdrive Signoff in High-Performance and Low-Power ICs10.362015
SI for free: machine learning of interconnect coupling delay and transition effects110.682015
A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction110.572015
3DIC benefit estimation and implementation guidance from 2DIC implementation70.582015
ORION3.0: A Comprehensive NoC Router Estimation Tool280.892015
Methodology for electromigration signoff in the presence of adaptive voltage scaling10.372014
A deep learning methodology to proliferate golden signoff timing70.602014
The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap50.532014
OCV-aware top-level clock tree optimization60.532014
Optimal reliability-constrained overdrive frequency selection in multicore systems30.462014
ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap100.702014
Learning-Based Approximation Of Interconnect Delay And Slew In Signoff Timing Tools50.542013
Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop insertion40.422013
Enhanced metamodeling techniques for high-dimensional IC design estimation problems100.802013
Explicit modeling of control and data for improved NoC router estimation301.352012
Redefining the Role of the CPU in the Era of CPU-GPU Integration90.502012
The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future763.422011