Name
Abstract | ||
|---|---|---|
An innovative 3D physical design exploration methodology for Tree-based FPGA architecture is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a multidimensional network with the logic unites and switch blocks placed at different levels, using a Butterfly-Fat Tree network topology. A 3D physical design exploration methodology leverage on Through Silicon Via (TSVs) using a horizontal break-point to re-distribute the Tree interconnects into multiple stacked active silicon layers proposed in this paper. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1145/2483028.2483130 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
horizontal break-point,butterfly-fat tree network topology,different level,tree-based fpga architecture,multidimensional network,tree interconnects,active silicon layer,logic unites,silicon via,physical design exploration methodology,tsv | Computer architecture,Multidimensional network,Computer science,Electronic engineering,Network topology,Through-silicon via,3d design,Fpga architecture,Physical design | Conference |
Citations | PageRank | References |
1 | 0.38 | 6 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vinod Pangracious | 1 | 41 | 8.11 |
| Emna Amouri | 2 | 39 | 7.83 |
| Habib Mehrez | 3 | 200 | 39.21 |
| Zied Marrakchi | 4 | 152 | 28.68 |