Emna Amouri - Citegraph

Author Info

Name	Affiliation	Papers
EMNA AMOURI	UPMC, Sorbonne University, Paris, France	19
Collaborators	Citations	PageRank
19	39	7.83
Referers	Referees	References
71	258	189

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100258

Publications (19 rows)

Collaborators (19 rows)

Referers (71 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support	0	0.34	2017
On Exploiting Partitioning-Based Placement Approach for Performances Improvement of 3D FPGA	1	0.35	2017
Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires.	3	0.40	2016
Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance.	1	0.36	2016
Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization	0	0.34	2016
Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA	0	0.34	2015
Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization.	3	0.41	2015
Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation	1	0.36	2014
Architecture level optimization of 3-dimensional tree-based FPGA.	1	0.36	2014
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA.	1	0.36	2014
Physical design exploration of 3D tree-based FPGA architecture	1	0.38	2013
Impact of dual placement and routing on WDDL netlist security in FPGA	1	0.36	2013
A defect-tolerant cluster in a mesh SRAM-based FPGA.	2	0.39	2013
Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture	3	0.41	2013
Performance analysis and optimization of high density tree-based 3d multilevel FPGA	8	0.93	2013
Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA	0	0.34	2011
Controlled Placement And Routing Techniques To Improve Timing Balance Of Wddl Designs In Mesh-Based Fpga	0	0.34	2010
Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing	2	0.42	2009
Efficient tree topology for FPGA interconnect network	11	0.65	2008

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