Name
Abstract | ||
|---|---|---|
This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. We demonstrate that these interconnects abstract the interconnect details and provide predictability in the data transfer, which are desirable not only for the functional domain but also for the test application. The proposed wrapper is implemented in VHDL and integrated to the 脝thereal NoC. The results show the impact of of bandwidth in the core test time. The wrapper area and core test time are compared with a wrapper design for dedicated TAM. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ETS.2006.48 | European Test Symposium |
Keywords | Field | DocType |
integrated circuit design,integrated circuit interconnections,integrated circuit testing,system-on-chip,Ethereal NoC,VHDL,interconnect wrapper design,networks-on-chip,on-chip protocol,test access mechanism | System on a chip,Data transmission,System testing,Computer science,Network on a chip,Electronic engineering,Real-time computing,Bandwidth (signal processing),Integrated circuit design,VHDL,Scalability,Embedded system | Conference |
ISSN | ISBN | Citations |
1530-1877 | 0-7695-2566-0 | 25 |
PageRank | References | Authors |
1.25 | 8 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alexandre M. Amory | 1 | 113 | 15.56 |
| Kees G. W. Goossens | 2 | 2050 | 131.83 |
| Erik Jan Marinissen | 3 | 2053 | 170.58 |
| Marcelo Lubaszewski | 4 | 483 | 47.66 |
| Fernando Moraes | 5 | 720 | 43.62 |