| Evaluation Of The Soft Error Assessment Consistency Of A Jit-Based Virtual Platform Simulator | 1 | 0.41 | 2021 |
| Memphis: a framework for heterogeneous many-core SoCs generation and validation | 2 | 0.38 | 2019 |
| A Framework for Heterogeneous Many-core SoCs Generation | 0 | 0.34 | 2019 |
| A Hierarchical and Distributed Fault Tolerant Proposal for NoC-Based MPSoCs. | 0 | 0.34 | 2018 |
| BAT-Hermes: A transition-signaling bundled-data NoC router | 3 | 0.44 | 2015 |
| A digitally controlled oscillator for fine-grained local clock generators in MPSoCs | 0 | 0.34 | 2015 |
| A monitored NoC with runtime path adaptation | 0 | 0.34 | 2014 |
| Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach | 16 | 0.59 | 2013 |
| Topology-agnostic fault-tolerant NoC routing method | 22 | 0.92 | 2013 |
| Enabling Adaptive Techniques in Heterogeneous MPSoCs Based on Virtualization | 1 | 0.36 | 2012 |
| A generic FPGA emulation framework | 1 | 0.46 | 2012 |
| CAFES: A framework for intrachip application modeling and communication architecture design | 6 | 0.53 | 2011 |
| A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms | 5 | 0.45 | 2011 |
| Hermes-a - an asynchronous NoC router with distributed routing | 6 | 0.51 | 2010 |
| Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area | 2 | 0.50 | 2009 |
| Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs | 13 | 0.67 | 2009 |
| Increasing NoC power estimation accuracy through a rate-based model | 5 | 0.43 | 2009 |
| A 10 Gbps OTN Framer Implementation Targeting FPGA Devices | 1 | 0.35 | 2009 |
| Hemps - A Framework For Noc-Based Mpsoc Generation | 18 | 0.88 | 2009 |
| MOTIM: an industrial application using nocs | 0 | 0.34 | 2008 |
| Validation of executable application models mapped onto network-on-chip platforms | 10 | 0.71 | 2008 |
| A simplified executable model to evaluate latency and throughput of networks-on-chip | 9 | 0.58 | 2008 |
| Congestion-aware task mapping in heterogeneous MPSoCs | 41 | 1.36 | 2008 |
| MultiNoC: A Multiprocessing System Enabled by a Network on Chip | 3 | 0.55 | 2007 |
| Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload | 7 | 0.55 | 2007 |
| Communication Models in Networks-on-Chip | 5 | 0.45 | 2007 |
| Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs | 74 | 2.50 | 2007 |
| SCAFFI: An intrachip FPGA asynchronous interface based on hard macros | 16 | 0.90 | 2007 |
| DfT for the Reuse of Networks-on-Chip as Test Access Mechanism | 10 | 0.52 | 2007 |
| MOTIM - A Scalable Architecture for Ethernet Switches | 4 | 0.45 | 2007 |
| SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems | 0 | 0.34 | 2007 |
| Adaptive coding in networks-on-chip: transition activity reduction versus power overhead of the codec circuitry | 6 | 0.52 | 2006 |
| Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism | 25 | 1.25 | 2006 |
| Reconfigurable Systems Enabled by a Network-on-Chip | 3 | 0.42 | 2006 |
| MAIA: a framework for networks on chip generation and verification | 26 | 1.62 | 2005 |
| Current mask generation: a transistor level security against DPA attacks | 9 | 0.67 | 2005 |
| Virtual channels in networks on chip: implementation and evaluation on hermes NoC | 37 | 1.83 | 2005 |
| Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation | 8 | 0.75 | 2005 |
| Traffic generation and performance evaluation for mesh-based NoCs | 17 | 0.82 | 2005 |
| Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture | 2 | 0.43 | 2005 |
| Reducing test time with processor reuse in network-on-chip based systems | 11 | 0.74 | 2004 |
| HERMES: an infrastructure for low area overhead packet-switching networks on chip | 261 | 12.15 | 2004 |
| PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems | 14 | 0.88 | 2004 |
| Design and Prototyping of Direct Torque Control of Induction Motors in FPGAs | 5 | 1.21 | 2003 |
| From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study | 15 | 1.86 | 2003 |
