Name
Abstract | ||
|---|---|---|
The goal of fault diagnosis is to identify the causes of device failures. Different techniques have been proposed for stuck-at fault diagnosis in combinational as well as sequential circuits. On the other side, diagnosis of delay faults has received attention for the first category of circuits, but not for synchronous sequential circuits. So, this paper concerns with delay fault diagnosis in non-scan circuits. The principle of the proposed method, based on a path tracing algorithm, is first given. Next, new concepts for improving path tracing in the proposed diagnosis process (identification of self-masking) are also presented. As the method is based on path tracing through the sequential circuit, gate delay faults as well as path delay faults are considered and may be located in a faulty machine. Results of experiments on ISCAS-89 sequential benchmark circuits are finally discussed. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1016/0167-9260(95)00013-7 | Integration |
Keywords | Field | DocType |
fault diagnosis,sequential circuit,delay fault diagnosis,synchronous sequential circuits,delay fault,sequential circuits | Digital electronics,Sequential logic,Computer science,Path tracing,Path delay,Real-time computing,Electronic engineering,Synchronous circuit,Critical path method,Electronic circuit,Integrated circuit | Journal |
Volume | Issue | ISSN |
19 | 3 | Integration, the VLSI Journal |
Citations | PageRank | References |
3 | 0.49 | 24 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| P. Girard | 1 | 478 | 41.91 |
| C. Landrault | 2 | 93 | 31.86 |
| S. Pravossoudovitch | 3 | 689 | 54.12 |
| B. Rodriguez | 4 | 10 | 1.34 |