P. Girard - Citegraph

Author Info

Name	Affiliation	Papers
P. GIRARD	UNIV MONTPELLIER 2,LAB INFORMAT ROBOT & MICROELECTR MONTPELLIER,CNRS,UMR 9928,161 RUE ADA,F-34392 MONTPELLIER 05,FRANCE	51
Collaborators	Citations	PageRank
93	478	41.91
Referers	Referees	References
705	665	571

Search Limit

100705

Publications (51 rows)

Collaborators (93 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing	0	0.34	2013
Evaluation of test algorithms stress effect on SRAMs under neutron radiation	0	0.34	2012
Power Supply Noise Sensor Based on Timing Uncertainty Measurements	1	0.50	2012
Peak Power Estimation: A Case Study on CPU Cores	1	0.48	2012
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits	4	0.53	2011
Failure Analysis and Test Solutions for Low-Power SRAMs	1	0.38	2011
On the Modeling of Gate Delay Faults by Means of Transition Delay Faults	1	0.37	2011
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling	1	0.36	2011
Power-Aware Test Pattern Generation for At-Speed LOS Testing	0	0.34	2011
A Comprehensive System-on-Chip Logic Diagnosis	1	0.36	2010
A Memory Fault Simulator for Radiation-Induced Effects in SRAMs	2	0.73	2010
A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash	2	0.44	2009
Comprehensive bridging fault diagnosis based on the SLAT paradigm	0	0.34	2009
A case study on logic diagnosis for System-on-Chip	2	0.43	2009
SoC Yield Improvement: Redundant Architectures to the Rescue?	2	0.52	2008
An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing	0	0.34	2008
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction	9	0.65	2008
Yield Improvement, Fault-Tolerance to the Rescue?	4	0.90	2008
SoC Symbolic Simulation: a case study on delay fault testing	5	0.53	2008
Using TMR Architectures for Yield Improvement	20	1.65	2008
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs	1	0.36	2007
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit	2	0.42	2006
March iC-: An Improved Version of March C- for ADOFs Detection	16	1.10	2004
Power-Driven Routing-Constrained Scan Chain Design	1	0.37	2004
Requirements for Delay Testing of Look-Up Tables in SRAM-Based FPGAs	2	0.45	2003
Hardware Generation of Random Single Input Change Test Sequences	7	0.73	2002
On Using Efficient Test Sequences for BIST	12	0.68	2002
Test Power: a Big Issue in Large SOC Designs	15	0.81	2002
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences	10	0.74	2001
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator	39	2.03	2001
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores	71	3.12	2001
Low Power BIST by Filtering Non-Detecting Vectors	30	1.89	2000
An adjacency-based test pattern generator for low power BIST design	1	0.43	2000
Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures	26	1.66	2000
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity	20	1.77	1999
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption	33	2.08	1999
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation	23	1.31	1999
On Calculating Efficient LFSR Seeds for Built-In Self Test	36	2.94	1999
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits	1	0.35	1999
Low power BIST by filtering non-detecting vectors.	0	0.34	1999
A BIST Structure to Test Delay Faults in a Scan Environment	3	0.47	1998
A Ring Architecture Strategy for BIST Test Pattern Generation	11	0.81	1998
A non-iterative gate resizing algorithm for high reduction in power consumption	1	0.37	1997
On using machine learning for logic BIST	17	1.07	1997
A gate resizing technique for high reduction in power consumption	15	1.18	1997
DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits	1	0.39	1996
A new test pattern generation method for delay fault testing	4	0.39	1996
An advanced diagnostic method for delay faults in combinational faulty circuits	11	1.32	1995
A trace-based method for delay fault diagnosis in synchronous sequential circuits	3	0.50	1995
Delay fault diagnosis in sequential circuits based on path tracing	3	0.49	1995

1
2
50 / page