Name
Abstract | ||
|---|---|---|
This paper proposes a technique for area-optimized FPGA technology mapping. The LURU algorithm maps a combinational circuit to a network of K-input lookup tables (LUTs). The LURU algorithm uses content addressable memory (CAM) to enable parallel pattern matching in a Boolean network. As a result, it is possible to quickly perform global searches within an entire Boolean network, thus increasing the quality of results compared to algorithms of local scope. To utilize CAM for the LURU algorithm, a circuit is described as a set of one dimensional text strings, each of which independently represents the topology of a portion of the circuit. The LURU algorithm was tested with specially partitioned circuits from the ISCAS '85 set of combinational benchmarks. These results are compared with results obtained from the mapping algorithms FlowMap and CutMap. It is demonstrated that using LURU leads to an average of 25% area improvement over both FlowMap and CutMap. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ICECS.2004.1399752 | ICECS 2004: 11th IEEE International Conference on Electronics, Circuits and Systems |
Keywords | DocType | Citations |
content addressable memory,lookup table,network topology,logic design,field programmable gate arrays,combinational circuits,boolean network,pattern matching,combinational circuit | Conference | 2 |
PageRank | References | Authors |
0.41 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Joshua M. Lucas | 1 | 2 | 1.09 |
| Raymond R. Hoare | 2 | 114 | 14.40 |
| Ivan S. Kourtev | 3 | 56 | 7.96 |
| Alex K. Jones | 4 | 578 | 61.61 |