| Multi-Phase Rotary Clock Synchronization of Level-Sensitive Circuits | 2 | 0.38 | 2009 |
| Delay insertion method in clock skew scheduling | 22 | 1.00 | 2006 |
| Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM) | 0 | 0.34 | 2006 |
| Performance metrics for asynchronous digital circuits applicable to computer-aided design | 0 | 0.34 | 2004 |
| A 64-way VLIW/SIMD FPGA Architecture and Design Flow | 6 | 0.78 | 2004 |
| Substrate coupling in digital circuits in mixed-signal smart-power systems | 7 | 1.01 | 2004 |
| LURU: global-scope FPGA technology mapping with content-addressable memories. | 2 | 0.41 | 2004 |
| Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits | 6 | 0.73 | 2004 |
| Performance improvement of edge-triggered sequential circuits. | 1 | 0.39 | 2004 |
| Advanced timing of level-sensitive sequential circuits. | 0 | 0.34 | 2004 |
| Short Courses in System-on-a-Chip (SoC) Design | 1 | 0.39 | 2003 |
| Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew | 2 | 0.43 | 2002 |
| Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling | 3 | 0.47 | 2002 |
| Demonstration Of Speed Enhancements On An Industrial Circuit Through Application Of Non-Zero Clock Skew Scheduling | 3 | 0.47 | 2001 |
| Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems | 1 | 0.48 | 1999 |
