Name
Abstract | ||
|---|---|---|
This paper describes the design and evaluation of a massively parallel processor base on Matrix architecture which is suitable for portable multimedia applications. The proposed architecture in this paper achieves 40 GOPS of 16-bit fixed-point additions at 200 MHz clock frequency and 250 mW power dissipation. In addition, 1 M-bit SRAM for data registers and 2,048 2-bit processing elements connected by a flexible switching network are integrated in 3.1 mm(2) in 90 nm low-power CMOS technology. The energy-efficient Matrix architecture supports 2,048-way parallel operations and the programmable functions required for multimedia SoCs. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1093/ietele/e89-c.11.1512 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | DocType | Volume |
massively parallel processor, SIMD, fine-grained ALU, wideband bus | Journal | E89C |
Issue | ISSN | Citations |
11 | 0916-8524 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Toru Shimizu | 1 | 41 | 9.45 |
| Masami Nakajima | 2 | 61 | 12.45 |
| Masahiro Kainaga | 3 | 31 | 2.66 |