A 20uA/MHz at 200MHz microcontroller with low power memory access scheme for small sensing nodes | 1 | 0.40 | 2016 |
A scalable massively parallel processor for real-time image processing | 5 | 0.60 | 2010 |
Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications | 5 | 0.69 | 2009 |
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture | 14 | 1.67 | 2007 |
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor | 7 | 0.74 | 2007 |
Design And Evaluation Of A Massively Parallel Processor Based On Matrix Architecture | 0 | 0.34 | 2006 |
A 40GOPS 250mW massively parallel processor based on matrix architecture | 22 | 6.07 | 2006 |
Implementation Of Face Recognition Processing Using An Embedded Processor | 0 | 0.34 | 2005 |
Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy | 2 | 0.54 | 1996 |
Design of multiple-valued linear digital circuits for highly parallel k-ary operations | 0 | 0.34 | 1994 |
Design of multiple-valued linear digital circuits for highly parallel unary operations | 5 | 0.73 | 1993 |