Name
Abstract | ||
|---|---|---|
This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tasks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we are able to enhance the testability of circuits with very little overheads on design area and execution time |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/EDTC.1994.326814 | EDAC-ETC-EUROASIC |
Keywords | DocType | Citations |
benchmark circuits,scheduling,logic cad,goodness measure,circuit testability,data path synthesis procedure,total execution time,c implementation,allocation tasks,stepwise refinement synthesis algorithm,point to point interconnection style architecture,logic design,synthesis for testability,scheduling tasks,design for testability,high level synthesis,design area,logic testing,rule of thumb | Conference | 2 |
PageRank | References | Authors |
0.37 | 6 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Taewhan Kim | 1 | 1087 | 113.31 |
| Ki-seok Chung | 2 | 189 | 18.76 |
| Chien-liang Liu | 3 | 169 | 18.94 |