Ki-seok Chung - Citegraph

Author Info

Name	Affiliation	Papers
KI-SEOK CHUNG	Daelim Coll, Div Elect Informat & Commun, Seoul, South Korea	34
Collaborators	Citations	PageRank
39	189	18.76
Referers	Referees	References
493	606	282

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100606

Publications (34 rows)

Collaborators (39 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Quality of service-aware dynamic voltage and frequency scaling for embedded GPUs	13	0.71	2015
Design of OpenCL framework for embedded multi-core processors	1	0.39	2014
A Parallelization Technique with Integrated Multi-Threading for Video Decoding on Multi-core Systems.	11	2.30	2013
Dynamic Power Management Technique for Multicore Based Embedded Mobile Devices	5	0.45	2013
Dynamic voltage and frequency scaling scheme for an adaptive LDPC decoder using SNR estimation.	10	0.43	2013
Multi-threaded syntax element partitioning for parallel entropy decoding.	4	0.69	2011
A Test Method for Power Management of SoC-based Microprocessors	1	0.36	2011
Parallel LDPC decoding using CUDA and OpenMP.	25	0.48	2011
Overlapped message passing technique with resource sharing for high speed CMMB LDPC decoder	3	0.70	2011
A Technique for Fast Process Creation Based on Creation Location.	0	0.34	2011
An adaptive low-power LDPC decoder using SNR estimation.	25	0.54	2011
Stage-based frame-partitioned parallelization of H.264/AVC decoding	5	0.47	2010
A predictive dynamic power management technique for embedded mobile devices	11	0.74	2010
Thermal sensor allocation and placement for reconfigurable systems	5	0.48	2009
Performance evaluation of on-chip interconnect IP using CBR traffic generator model	0	0.34	2009
A novel SoC platform based multi-IP verification and performance measurement	0	0.34	2009
Low Power Mac Design With Variable Precision Support	1	0.36	2009
Implementation of IEEE802.11a software defined receiver on chip multi-processor architecture using OpenMP	0	0.34	2009
Memory efficient multi-rate regular LDPC decoder for CMMB	8	0.72	2009
Thermal-Aware High-Level Synthesis Based on Network Flow Method	8	0.52	2009
Optimisation of RunBefore decoder and first one detector for MPEG-4 AVC/H.264 CAVLC decoding	1	0.48	2009
Predictive power aware management for embedded mobile devices	1	0.36	2008
A unified power measurement and management platform for pipelined MPSoC executions	0	0.34	2008
Design of Low Power MAC Operator with Dual Precision Mode	1	0.36	2007
Profile-based optimal intra-task voltage scheduling for hard real-time applications	30	1.68	2004
Properties Of Al/Bata2o6/Gan Mis Structure	0	0.34	2003
A complete model for glitch analysis in logic circuits	1	0.47	2002
Synthesis and Optimization of Combinational Interface Circuits	0	0.34	2002
G-vector: A New Model for Glitch Analysis in Logic Circuits	1	0.36	2001
A static estimation technique of power sensitivity in logic circuits	1	0.37	2001
Behavioral-level partitioning for low power design in control-dominated application	1	0.34	2000
Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction	6	0.52	1998
An algorithm for synthesis of system-level interface circuits	8	0.77	1996
A stepwise refinement data path synthesis procedure for easy testability	2	0.37	1994