Name
Abstract | ||
|---|---|---|
Many Boolean functions are efficiently represented as Ordered Binary Decision Diagrams (OBDDS). However, the order in which variables appear in an OBDD can significantly affect their required memory space. In this paper we present a functional approach to generate orderings for representing functions. We develop a cost function which closely mimics the OBDD operations and can be quickly computed. Using the cost as a metric for an ordering, we use an annealing procedure to arrive at “good” variable orderings. We compare the results obtained by simulated annealing to orderings generated from heuristics that use circuit topology to arrive at a variable ordering. |
Year | DOI | Venue |
|---|---|---|
1992 | 10.1109/DAC.1992.227810 | DAC |
Keywords | Field | DocType |
logic design,simulated annealing,annealing procedure,binary decision diagram,circuit topology,functional,symbolic representations | Simulated annealing,Logic synthesis,Functional approach,Computer science,Algorithm,Binary decision diagram,Heuristics,Topology (electrical circuits) | Conference |
ISSN | ISBN | Citations |
0738-100X | 0-89791-516-X | 32 |
PageRank | References | Authors |
4.29 | 12 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. R. Mercer | 1 | 353 | 47.36 |
| R. Kapur | 2 | 33 | 4.66 |
| D. E. Ross | 3 | 36 | 4.74 |