| Directed-Binary Search in Logic BIST Diagnostics | 3 | 0.55 | 2002 |
| On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction | 4 | 0.63 | 2000 |
| Using target faults to detect non-target defects | 21 | 2.11 | 1996 |
| Iddq Testing for High Performance CMOS - The Next Ten Years | 30 | 4.11 | 1996 |
| Improved sequential ATPG using functional observation information and new justification methods | 8 | 0.90 | 1995 |
| Enhanced testing performance via unbiased test sets | 3 | 0.78 | 1995 |
| Limitations in predicting defect level based on stuck-at fault coverage | 20 | 1.90 | 1994 |
| Least Upper Bounds on OBDD Sizes | 12 | 0.85 | 1994 |
| Bounding signal probabilities for testability measurement using conditional syndromes | 5 | 0.55 | 1992 |
| An efficient delay test generation system for combinational logic circuits | 28 | 2.20 | 1992 |
| Functional approaches to generating orderings for efficient symbolic representations | 32 | 4.29 | 1992 |
| The interdependence between delay-optimization of synthesized networks and testing | 40 | 9.97 | 1991 |
| Guest Editorial: ITC 20th Anniversary | 0 | 0.34 | 1990 |
| A deterministic approach to adjacency testing for delay faults | 14 | 1.36 | 1989 |
| D3FS: a demand driven deductive fault simulator | 0 | 0.34 | 1988 |
| A method of delay fault test generation | 51 | 7.57 | 1988 |
| Statistical delay fault coverage and defect level for delay faults | 51 | 4.49 | 1988 |
| Demand driven simulation: BACKSIM | 29 | 3.55 | 1987 |
| Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits | 2 | 0.86 | 1986 |
