Title
Long-Retention-Time, High-Speed Dram Array With 12-F-2 Twin Cell For Sub 1-V Operation
Abstract
DRAM-cell array with 12-F-2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at I V and keeps the retention time of the single-cell array at 0.4 V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4 V.
Year
DOI
Venue
2007
10.1093/ietele/e90-c.4.758
IEICE TRANSACTIONS ON ELECTRONICS
Keywords
DocType
Volume
twin-cell DRAM array, write time, low voltage RAM, retention time, and plate-driven cell
Journal
E90C
Issue
ISSN
Citations 
4
1745-1353
0
PageRank 
References 
Authors
0.34
0
7
Name
Order
Citations
PageRank
Riichiro Takemura14426.44
Kiyoo Itoh27823.29
Tomonori Sekiguchi3173.74
Satoru Akiyama401.35
Satoru Hanzawa5196.53
Kazuhiko Kajigaya601.01
Takayuki Kawahara7318103.32