Name
Abstract | ||
|---|---|---|
An efficient approach to Nearest Neighbor classification is presented, which improves performance by exploiting the ability of superscalar processors to issue multiple instructions per cycle and by using the memory hierarchy adequately. This is accomplished by the use of floating-point arithmetic which outperforms integer arithmetic, and block (tiled) algorithms which exploit the data locality of programs allowing an efficient use of the data stored in the cache memory. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1007/3-540-32390-2_19 | Computer Recognition Systems, Proceedings |
Keywords | Field | DocType |
floating point arithmetic,cache memory,instructions per cycle | Instructions per cycle,k-nearest neighbors algorithm,Locality,Integer arithmetic,Memory hierarchy,CPU cache,Computer science,Parallel computing,Exploit,Superscalar | Conference |
ISSN | Citations | PageRank |
1615-3871 | 0 | 0.34 |
References | Authors | |
16 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| José R. Herrero | 1 | 94 | 16.90 |
| Juan J. Navarro | 2 | 323 | 42.90 |