Juan J. Navarro - Citegraph

Author Info

Name	Affiliation	Papers
JUAN J. NAVARRO	Department of Computer Architecture, Universitat Politècnica de Catalunya, Gran Capità s/n, Modul D6, E-08034 Barcelona, Spain	41
Collaborators	Citations	PageRank
40	323	42.90
Referers	Referees	References
605	516	385

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100605

Publications (41 rows)

Collaborators (40 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Reusing cached schedules in an out-of-order processor with in-order issue logic	3	0.38	2009
Hypermatrix oriented supernode amalgamation	1	0.39	2008
Analysis of a sparse hypermatrix Cholesky with fixed-sized blocking	1	0.36	2007
Exploiting computer resources for fast nearest neighbor classification	8	0.50	2007
Using non-canonical array layouts in dense matrix operations	1	0.42	2006
Compiler-optimized kernels: an efficient alternative to hand-coded inner kernels	4	0.43	2006
A study on load imbalance in parallel hypermatrix multiplication using OpenMP	0	0.34	2005
Adapting linear algebra codes to the memory hierarchy using a hypermatrix scheme	1	0.36	2005
Efficient Implementation of Nearest Neighbor Classification	0	0.34	2005
Optimization of a statically partitioned hypermatrix sparse cholesky factorization	1	0.36	2004
Automatic Benchmarking and Optimization of Codes: An Experience with Numerical Kernels	7	0.60	2003
Building Software Via Shared Knowledge	0	0.34	2003
CC-Radix: a Cache Conscious Sorting Based on Radix sort	11	1.06	2003
Improving Performance of Hypermatrix Cholesky Factorization	9	0.58	2003
Case study: Memory conscious parallel sorting	1	0.37	2002
The effect of local sort on parallel sorting algorithms	1	0.37	2002
Fast parallel in-memory 64-bit sorting	7	0.65	2001
Sorting on the SGI Origin 2000: comparing MPI and shared memory implementations	0	0.34	1999
Communication conscious radix sort	8	0.80	1999
Dynamic history-length fitting: a third level of adaptivity for branch prediction	50	4.23	1998
Data caches for superscalar processors	27	1.47	1997
Block algorithms for sparse matrix computations on high performance workstations	12	1.72	1996
The difference-bit cache	17	1.28	1996
Data prefetching and multilevel blocking for linear algebra operations	8	0.75	1996
Vector and Parallel Interpolation by Natural Cubic Splines and B-Splines	1	0.41	1996
Review of general and Toeplitz vector bidiagonal solvers	8	0.67	1996
Performance on Distributed Memory Multicomputers of Domain Decomposition Solvers	0	0.34	1995
A Generalized Criterion for the Early Termination of R-Cyclic Reduction and Divide and Conquer for Recurrences	0	0.34	1995
A generalized vision of some parallel bidiagonal systems solvers	2	0.41	1994
MOB forms: a class of multilevel block algorithms for dense linear algebra operations	24	4.07	1994
A Parallel Tridiagonal Solver For Vector Uniprocessors	2	0.41	1993
Spike algorithm with savings for strictly diagonal dominant tridiagonal systems	2	0.45	1993
A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units	5	0.77	1992
Increasing the number of strides for conflict-free vector access	40	5.99	1992
Performance evaluation of transputer systems with linear algebra problems	0	0.34	1991
Mapping QR decomposition of banded matrix on a 1D systolic array with data contraflow and pipelined functional units	1	0.40	1991
Conflict-Free Strides for Vectors in Matched Memories	2	0.38	1991
Transformation of systolic algorithms for interleaving partitions	0	0.34	1991
Systematic hardware adaptation of systolic algorithms	4	0.72	1989
Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors	51	7.14	1987
Solving Matrix Problems with No Size Restriction on a Systolic Array Processor	3	1.28	1986