Name
Title | ||
|---|---|---|
Optimizing and comparing CMOS implementations of the C-element in 65nm technology: self-timed ring case |
Abstract | ||
|---|---|---|
Self-timed rings are a promising approach for designing high-speed serial links or clock generators. This study focuses on the ring stage components - a C-element and an inverter - and compares the performances of different implementations of this component in terms of speed, power consumption and phase noise. We also proposed a new self-timed ring stage - only composed by a C-element with complementary outputs - which allows us to increase the maximum speed of 25% and reduce the power consumption of 60% at the maximum frequency. All the electrical simulations and results have been performed using a CMOS 65nm technology from STMicroelectronics. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1007/978-3-642-17752-1_14 | PATMOS |
Keywords | Field | DocType |
clock generator,electrical simulation,ring stage component,maximum frequency,self-timed ring case,cmos implementation,self-timed ring,different implementation,power consumption,complementary output,new self-timed ring stage,maximum speed,phase noise | Inverter,Flicker noise,Computer science,Phase noise,Electronic engineering,Implementation,CMOS,Real-time computing,Electrical engineering,Power consumption,C-element | Conference |
Volume | ISSN | ISBN |
6448 | 0302-9743 | 3-642-17751-4 |
Citations | PageRank | References |
1 | 0.37 | 11 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Oussama Elissati | 1 | 3 | 1.76 |
| Eslam Yahya | 2 | 25 | 5.94 |
| Sébastien Rieubon | 3 | 3 | 1.44 |
| Laurent Fesquet | 4 | 289 | 49.04 |