Eslam Yahya - Citegraph

Author Info

Name	Affiliation	Papers
ESLAM YAHYA	TIMA Laboratory, Grenoble, France and Banha High Institute of Technology, Banha, Egypt	14
Collaborators	Citations	PageRank
21	25	5.94
Referers	Referees	References
60	195	81

Search Limit

100195

Publications (14 rows)

Collaborators (21 rows)

Referers (60 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation.	0	0.34	2018
Power Efficient Aes Core For Iot Constrained Devices Implemented In 130nm Cmos	0	0.34	2017
Presenting a synchronous — Asynchronous standard cell library based on 7nm FinFET technology	0	0.34	2016
ERSUT: A Self-Healing Architecture for Mitigating PVT Variations Without Pipeline Flushing.	2	0.41	2016
Library based macro-modeling methodology for Through Silicon Via (TSV) arbitrary arrays	1	0.48	2015
Deadlock Detection In Conditional Asynchronous Circuits Under Mismatched Branch Selection	0	0.34	2015
Different scenarios for estimating coupling capacitances of through silicon via (TSV) arrays	2	0.38	2015
Coupling Capacitance Extraction In Through-Silicon Via (Tsv) Arrays	0	0.34	2015
Optimizing and comparing CMOS implementations of the C-element in 65nm technology: self-timed ring case	1	0.37	2010
Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks.	0	0.34	2010
Asynchronous design: A promising paradigm for electronic circuits and systems	7	0.69	2009
Asynchronous Linear Pipelines: An efficient-optimal pipelining algorithm.	1	0.39	2008
QDI latches characteristics and asynchronous linear-pipeline performance analysis	8	0.67	2006
Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA	3	0.51	2003

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