Paper Info
Title
Using partial reconfiguration and message passing to enable FPGA-based generic computing platforms
Abstract
Partial reconfiguration (PR) is an FPGA feature that allows the modification of certain parts of an FPGA while the rest of the system continues to operate without disruption. This distinctive characteristic of FPGAs has many potential benefits but also challenges. The lack of good CAD tools and the deep hardware knowledge requirement result in a hard-to-use feature. In this paper, the new partition-based Xilinx PR flow is used to incorporate PR within our MPI-based message-passing framework to allow hardware designers to create template bitstreams, which are predesigned, prerouted, generic bitstreams that can be reused for multiple applications. As an example of the generality of this approach, four different applications that use the same template bitstream are run consecutively, with a PR operation performed at the beginning of each application to instantiate the desired application engine. We demonstrate a simplified, reusable, high-level, and portable PR interface for X86-FPGA hybrid machines. PR issues such as local resets of reconfigurable modules and context saving and restoring are addressed in this paper followed by some examples and preliminary PR overhead measurements.
Year
DOI
Venue
2012
10.1155/2012/127302
Int. J. Reconfig. Comp.
Keywords
Field
DocType
deep hardware knowledge requirement,pr issue,pr operation,generic bitstreams,different application,preliminary pr overhead measurement,generic computing platform,partial reconfiguration,application engine,fpga feature,new partition-based xilinx pr,portable pr interface
Cad tools,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Bitstream,Generality,Control reconfiguration,Message passing,Embedded system
Journal
Volume
Citations 
PageRank 
2012,
5
0.64
References 
Authors
11
4
Name
Order
Citations
PageRank
Manuel Saldaña1625.96
Arun Patel2463.48
Hao Jun Liu3121.47
Paul Chow4868119.97