Name
Abstract | ||
|---|---|---|
The test cost of heterogeneous ICs has significantly increased. So, the definition of relevant test methods and efficient test stimuli are becoming critical research orientations for semiconductor manufacturers. The authors of this article propose decreasing the manufacturing test cost of analog and mixed-signal (AMS) and RF SoCs by automatically qualifying and optimizing the existing test set. Their computer-aided test (CAT) tool, Plasma, uses fault injection and a fault simulation technique to perform test qualification and generation. This tool reduces both test time and test equipment cost using a high-level fault model. After discussing the advantages using behavioral fault models, the authors present a method that lets them decrease overall simulation time. This method reduces the number of simulated fault-free models, thanks to a normal estimation. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/MDT.2008.7 | IEEE Design & Test of Computers |
Keywords | Field | DocType |
existing test set,test qualification,relevant test method,efficient test stimulus,test time,test cost,rf systems,behavioral fault model,decreasing test qualification time,manufacturing test cost,test equipment cost,computer-aided test,soc,integrated circuit design,generation time,behavior modeling,fault model,behavioral modeling,system on chip | Automatic test pattern generation,System on a chip,Fault coverage,Computer science,Behavioral modeling,Electronic engineering,Test compression,Fault model,Fault injection,Test set | Journal |
Volume | Issue | ISSN |
25 | 1 | 0740-7475 |
Citations | PageRank | References |
1 | 0.43 | 7 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yves Joannon | 1 | 2 | 1.16 |
| Vincent Beroulle | 2 | 86 | 21.86 |
| Robach, C. | 3 | 208 | 36.30 |
| S. Tedjini | 4 | 34 | 15.44 |
| J. L. Carbonero | 5 | 14 | 3.21 |