| An In-Depth Vulnerability Analysis of RISC-V Micro-Architecture Against Fault Injection Attack | 0 | 0.34 | 2021 |
| Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism | 0 | 0.34 | 2021 |
| MaDMAN: Detection of Software Attacks Targeting Hardware Vulnerabilities | 0 | 0.34 | 2021 |
| Clock skew-based physical authentication protocol for 802.15.4 IR-UWB indoor positioning. | 0 | 0.34 | 2020 |
| Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems | 0 | 0.34 | 2020 |
| PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community | 1 | 0.45 | 2020 |
| High Level Fault Injection Method for Evaluating Critical System Parameter Ranges | 0 | 0.34 | 2020 |
| Machine Learning and Hardware security - Challenges and Opportunities -Invited Talk-. | 0 | 0.34 | 2020 |
| Analyzing Software Security Against Complex Fault Models with Frama-C Value Analysis | 0 | 0.34 | 2019 |
| An Optimized NS2 Module for UHF Passive RFID Systems | 0 | 0.34 | 2019 |
| On a Low Cost Fault Injection Framework for Security Assessment of Cyber-Physical Systems: Clock Glitch Attacks | 1 | 0.36 | 2019 |
| Security Evaluation with an Indoor UWB Localization Open Platform: Acknowledgment Attack Case Study | 0 | 0.34 | 2019 |
| Fault Injection on Hidden Registers in a RISC-V Rocket Processor and Software Countermeasures | 1 | 0.35 | 2019 |
| Cross-layer analysis of software fault models and countermeasures against hardware fault attacks in a RISC-V processor | 1 | 0.38 | 2019 |
| Restricting Switching Activity Using Logic Locking to Improve Power Analysis-Based Trojan Detection | 0 | 0.34 | 2019 |
| Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model | 5 | 0.45 | 2018 |
| The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks | 2 | 0.44 | 2018 |
| On the Importance of Analysing Microarchitecture for Accurate Software Fault Models | 2 | 0.45 | 2018 |
| Security Enhancements of a Mutual Authentication Protocol Used in a HF Full-Fledged RFID Tag. | 0 | 0.34 | 2018 |
| Time Modeling with NS2 in UHF RFID Anti-Collision Protocols | 1 | 0.38 | 2018 |
| ESCALATION: Leveraging Logic Masking to Facilitate Path-Delay-Based Hardware Trojan Detection Methods. | 1 | 0.37 | 2018 |
| ElectroMagnetic Attack Test Platform for Validating RFID Tag Architectures | 0 | 0.34 | 2018 |
| Guidelines for the Choice of a Wireless Secure Positioning and Communication System | 1 | 0.37 | 2018 |
| A global approach for the improvement of UHF RFID safety and security | 0 | 0.34 | 2017 |
| Analysis of laser-induced errors: RTL fault models versus layout locality characteristics. | 0 | 0.34 | 2016 |
| On the development of a new countermeasure based on a laser attack RTL fault model | 0 | 0.34 | 2016 |
| How logic masking can improve path delay analysis for Hardware Trojan detection | 0 | 0.34 | 2016 |
| Clock generator behavioral modeling for supply voltage glitch attack effects analysis. | 0 | 0.34 | 2016 |
| On fault injections for early security evaluation vs. laser-based attacks | 0 | 0.34 | 2016 |
| ECDSA Passive Attacks, Leakage Sources, and Common Design Mistakes. | 1 | 0.40 | 2016 |
| Validation of RTL laser fault injection model with respect to layout information | 2 | 0.38 | 2015 |
| Facilitating side channel analysis by obfuscation for Hardware Trojan detection | 0 | 0.34 | 2015 |
| Laser-Induced Fault Effects In Security-Dedicated Circuits | 3 | 0.53 | 2014 |
| A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks | 5 | 0.47 | 2014 |
| Voltage Glitch Attacks on Mixed-Signal Systems | 4 | 0.39 | 2014 |
| Evaluation of a new RFID system performance monitoring approach | 0 | 0.34 | 2012 |
| Towards middleware-based fault-tolerance in RFID systems | 0 | 0.34 | 2011 |
| Read rate profile monitoring for defect detection in RFID Systems. | 2 | 0.44 | 2011 |
| SystemC modeling of RFID systems for robustness analysis | 2 | 0.46 | 2011 |
| RFID System On-line Testing Based on the Evaluation of the Tags Read-Error-Rate | 7 | 1.28 | 2011 |
| Towards an unified IP verification and robustness analysis platform | 2 | 0.48 | 2011 |
| Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application | 7 | 0.85 | 2009 |
| Choice of a high-level fault model for the optimization of validation test set reused for manufacturing test | 1 | 0.39 | 2008 |
| Decreasing Test Qualification Time in AMS and RF Systems | 1 | 0.43 | 2008 |
| A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application | 3 | 0.40 | 2008 |
| Qualification Of Behavioral Level Design Validation For Ams & Rf Socs | 0 | 0.34 | 2007 |
| Impact Of Hardware Emulation On The Verification Quality Improvement | 2 | 0.53 | 2007 |
| Functional Verification of RTL Designs driven by Mutation Testing metrics | 13 | 0.78 | 2007 |
| Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip | 2 | 0.43 | 2007 |
| A DFT Architecture for Asynchronous Networks-on-Chip | 11 | 0.66 | 2006 |
