Name
Abstract | ||
|---|---|---|
Timing closure and power envelopes for contemporary multi-core chips with high speed clock networks make the clock distribution design a challenging task. Resonant rotary clocking is a novel clocking technology for multi-gigahertz rate clock generation that provides minimal power dissipation. Rotary clocking implementations can easily provide independent synchronization of multiple cores as well. The traditional rotary clock design involves a regular array topology of oscillatory rings. In this paper, the rotary clock networks are designed and implemented using a custom ring topology. Custom ring topologies are advantageous as they reduce the total tapping wirelength for the registers tapping onto the oscillatory rings. A maze router based algorithm is developed for the implementation of custom topology rotary rings. In experiments performed on UCLA IBM R1-R5 benchmark circuits with the Elmore delay model, an improvement of 11.04% for register tapping wirelength is achieved on average. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ICCD.2008.4751849 | 2008 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN |
Keywords | Field | DocType |
capacitance,topology,registers,power dissipation,chip,oscillators,synchronization | Synchronization,Computer science,Clock domain crossing,Parallel computing,Network topology,Electronic engineering,Router,Digital clock manager,Ring network,Elmore delay,Timing closure | Conference |
ISSN | Citations | PageRank |
1063-6404 | 1 | 0.37 |
References | Authors | |
8 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vinayak Honkote | 1 | 28 | 4.84 |
| Baris Taskin | 2 | 227 | 40.82 |