| Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems | 0 | 0.34 | 2021 |
| SnackNoC: Processing in the Communication Layer | 2 | 0.37 | 2020 |
| TSV Antennas for Multi-Band Wireless Communication | 1 | 0.38 | 2020 |
| Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking | 0 | 0.34 | 2020 |
| FinFET - Based Low Swing Rotary Traveling Wave Oscillators. | 0 | 0.34 | 2020 |
| Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation | 0 | 0.34 | 2019 |
| FOPAC : Flexible On-Chip Power and Clock | 0 | 0.34 | 2019 |
| Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis. | 0 | 0.34 | 2019 |
| Robust Low Power Clock Synchronization for Multi-Die Systems | 0 | 0.34 | 2019 |
| The Adiabatically Driven StrongARM Comparator. | 0 | 0.34 | 2019 |
| Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors. | 1 | 0.35 | 2019 |
| RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer | 1 | 0.36 | 2019 |
| SLECTS: Slew-Driven Clock Tree Synthesis | 0 | 0.34 | 2019 |
| On-chip wireless interconnect paradigm | 0 | 0.34 | 2019 |
| Low Voltage Clock Tree Synthesis with Local Gate Clusters | 0 | 0.34 | 2019 |
| Towards Cross-Framework Workload Analysis via Flexible Event-Driven Interfaces | 0 | 0.34 | 2018 |
| Towards Design Decisions for Genetic Algorithms in Clock Tree Synthesis | 0 | 0.34 | 2018 |
| Vertical Arbitration-Free 3-D NoCs. | 0 | 0.34 | 2018 |
| SynchroTrace: Synchronization-Aware Architecture-Agnostic Traces for Lightweight Multicore Simulation of CMP and HPC Workloads. | 3 | 0.38 | 2018 |
| Reconfigurable threshold logic gates using optoelectronic capacitors. | 0 | 0.34 | 2017 |
| A charge recovery logic system bus | 0 | 0.34 | 2017 |
| Stability Of Rotary Traveling Wave Oscillators Under Process Variations And Nbti | 0 | 0.34 | 2017 |
| Slew-down: analysis of slew relaxation for low-impact clock buffers | 0 | 0.34 | 2017 |
| Special issue on IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2016 | 0 | 0.34 | 2017 |
| Charge recovery implementation of an analog comparator: Initial results | 0 | 0.34 | 2017 |
| WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS | 0 | 0.34 | 2017 |
| Wireless NoCs Using Directional and Substrate Propagation Antennas | 0 | 0.34 | 2017 |
| Energy aware routing of multi-level Network-on-Chip traffic | 0 | 0.34 | 2016 |
| Wireless Network-on-Chip analysis of propagation technique for on-chip communication | 0 | 0.34 | 2016 |
| Design Methodology for Voltage-Scaled Clock Distribution Networks. | 1 | 0.37 | 2016 |
| ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design | 3 | 0.52 | 2015 |
| Enhanced Level Shifter For Multi-Voltage Operation | 2 | 0.39 | 2015 |
| Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping | 0 | 0.34 | 2015 |
| Synchrotrace: synchronization-aware architecture-agnostic traces for light-weight multicore simulation | 6 | 0.42 | 2015 |
| Locality-Aware Network Utilization Balancing in NoCs | 1 | 0.35 | 2015 |
| A wirelessly powered system with charge recovery logic | 1 | 0.41 | 2015 |
| Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression Modeling | 1 | 0.36 | 2015 |
| FinFET-Based Low-Swing Clocking | 5 | 0.48 | 2015 |
| Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation | 2 | 0.38 | 2015 |
| Frequency-centric resonant rotary clock distribution network design | 0 | 0.34 | 2014 |
| Range-based Dynamic Routing of Hierarchical On Chip Network Traffic | 2 | 0.37 | 2014 |
| Iterative skew minimization for low swing clocks. | 0 | 0.34 | 2014 |
| High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design | 3 | 0.41 | 2014 |
| Timing characterization of clock buffers for clock tree synthesis | 4 | 0.46 | 2014 |
| Multi-corner multi-voltage domain clock mesh design | 2 | 0.40 | 2013 |
| Skew-bounded low swing clock tree optimization | 4 | 0.46 | 2013 |
| Rotary traveling wave oscillator frequency division at nanoscale technologies | 0 | 0.34 | 2013 |
| A microcontroller-based embedded system design course with PSoC3 | 2 | 0.46 | 2013 |
| Resonant Frequency Divider Design Methodology For Dynamic Frequency Scaling | 0 | 0.34 | 2013 |
| Sparse-rotary oscillator array (SROA) design for power and skew reduction | 3 | 0.44 | 2013 |
