Name
Abstract | ||
|---|---|---|
The integration of different Intellectual Property (IP) cores to modern System-on-Chip (SoC) de- signs becomes more and more an important topic because of the benefits in the overall system performance and the design costs. In this paper we present a new generic framework consisting of a graphical user interface with an extendable highly parameterizable IP component library for con- venient SoC architecture entry, as well as software tools, which provide an automatic generation of fast cycle-accurate simulators for verification purposes and synthesizable HDL code for hardware synthesis. Because the communication of the single IP cores also plays an important role, our IP core library includes an open-source bus component, which is used in a case study design. Topics: System-on-a-chip: design and methodology, Case studies, FPGA-based design |
Year | Venue | Keywords |
|---|---|---|
2006 | CDES | graphic user interface,intellectual property,system performance,system on a chip,system on chip |
Field | DocType | Citations |
Rapid prototyping,Computer architecture,Architecture,System on a chip,Software,Graphical user interface,Intellectual property,Engineering,Hardware synthesis,Embedded system | Conference | 2 |
PageRank | References | Authors |
0.43 | 8 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dmitrij Kissler | 1 | 78 | 7.30 |
| Alexey Kupriyanov | 2 | 79 | 6.40 |
| Frank Hannig | 3 | 595 | 75.66 |
| Dirk Koch | 4 | 448 | 39.02 |
| Jürgen Teich | 5 | 2886 | 273.54 |