A holistic approach for tightly coupled reconfigurable parallel processors | 6 | 0.43 | 2009 |
Modeling of interconnection networks in massively parallel processor architectures | 3 | 0.45 | 2007 |
Efficient event-driven simulation of parallel processor architectures | 5 | 0.45 | 2007 |
Massively Parallel Processor Architectures: A Co-design Approach | 1 | 0.36 | 2007 |
A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template | 8 | 0.71 | 2006 |
A Generic Framework for Rapid Prototyping of System-on-Chip Designs | 2 | 0.43 | 2006 |
A Highly Parameterizable Parallel Processor Array Architecture | 40 | 2.35 | 2006 |
An Architecture Description Language for Massively Parallel Processor Architectures. | 5 | 0.53 | 2006 |
Co-Design of Massively Parallel Embedded Processor Architectures | 9 | 0.67 | 2005 |