Name
Abstract | ||
|---|---|---|
Microcode enables programmability of (micro) architectural structures to enhance functionality and to apply patches to an existing design. As more features get added to a CPU core, the area and power costs associated with microcode increase. A recent Intel internal design targeted at low power and small footprint has estimated the costs of the microcode ROM to approach 20% of the total die area (and associated power consumption). Therefore, it is desirable to apply compression techniques to microcode.Microcode poses unique challenges for compression due to the long instruction format, the hand-coded nature of the programs and the stringent performance requirements that require fast decompression. This paper describes techniques for microcode compression that achieve significant area and power savings, while presenting a streamlined architecture that enables high throughput within the constraints of a high performance CPU. The paper presents results for microcode compression on several commercial CPU designs which demonstrates compression ratios ranging from 50% to 62%. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ICCD.2006.4380816 | PROCEEDINGS 2006 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN |
Keywords | Field | DocType |
firmware,compression ratio,high throughput,cpu core | Microcode,Computer science,Parallel computing,Ranging,Compression ratio,Footprint,Throughput,Computer hardware,Cluster analysis,Multi-core processor,Firmware,Embedded system | Conference |
ISSN | Citations | PageRank |
1063-6404 | 2 | 0.38 |
References | Authors | |
11 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Edson Borin | 1 | 131 | 10.48 |
| Mauricio Breternitz Jr. | 2 | 15 | 2.76 |
| Youfeng Wu | 3 | 749 | 52.16 |
| Guido Araujo | 4 | 451 | 38.59 |