Edson Borin - Citegraph

Author Info

Name	Affiliation	Papers
EDSON BORIN	PSL - Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA 95054, USA	21
Collaborators	Citations	PageRank
35	131	10.48
Referers	Referees	References
312	704	315

Search Limit

100704

Publications (21 rows)

Collaborators (35 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
The Multi-Lane Capsule Network (MLCN).	0	0.34	2019
A Methodology for Optimization of Interpreters	0	0.34	2018
SHRINK: reducing the ISA complexity via instruction recycling	2	0.39	2015
Performance implications of dynamic memory allocators on transactional memory systems	8	0.51	2015
Microcode Compression Using Structured-Constrained Clustering	0	0.34	2014
Image Re-ranking Acceleration on GPUs	3	0.36	2013
Assessing computer performance with stocs	1	0.36	2013
An automatic energy consumption characterization of processors using ArchC	3	0.45	2013
An ArchC approach for automatic energy consumption characterization of processors	1	0.36	2012
Efficient Image Re-Ranking Computation on GPUs	3	0.37	2012
ACCGen: An Automatic ArchC Compiler Generator	3	0.39	2012
Structure-Constrained Microcode Compression	0	0.34	2011
LAR-CC: Large atomic regions with conditional commits	7	0.44	2011
A HW/SW co-designed heterogeneous multi-core virtual machine for energy-efficient general purpose computing	10	0.52	2011
Trace execution automata in dynamic binary translation	2	0.37	2010
TAO: two-level atomicity for dynamic binary optimizations	10	0.54	2010
Dynamic parallelization of single-threaded binary programs using speculative slicing	19	0.73	2009
Characterization of DBT overhead	11	0.65	2009
Software-Based Transparent and Comprehensive Control-Flow Error Detection	41	1.87	2006
Clustering-Based Microcode Compression	2	0.38	2006
Dynamic binary control-flow errors detection	5	0.44	2005