Paper Info
Title
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.
Abstract
This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The process scaling increases random variation that degrades SRAM operating margins, for which the proposed DW8T cell presents two features: half-VDD precharging write bitlines and dual write wordlines. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. The DW8T SRAM with the sequential writing technique improve a half-select bit error rate by 71% at the disturb worst corner (FS, 125 degrees C) and by 79% at a typical corner (CC, 25 degrees C) over the conventional 8T, respectively. We implemented a 256-Kb DW8T SRAM and a half-VDD generator on a single chip in a 40-nm CMOS process. The measurement results of the seven samples show that the proposed DW8T SRAM achieves a VDDmin of 600 mV and improves the average VDDmin by 367 mV compared to the conventional 8T SRAM. The measured leakage power can be reduced by 25%.
Year
DOI
Venue
2012
10.1109/ISQED.2012.6187538
ISQED
Keywords
Field
DocType
CMOS integrated circuits,SRAM chips,CMOS process,dual write wordlines,half-select bit error rate,half-select resilient dual write wordline 8T SRAM,leakage power,memory size 256 KByte,precharging write bitlines,sequential writing technique,size 40 nm,voltage 0.6 V,voltage 367 mV,8T,SRAM,disturb,half-select
Computer science,Leakage power,Electronic engineering,Real-time computing,Cmos process,Static random-access memory,Chip,CMOS,Bit error rate
Conference
ISSN
Citations 
PageRank 
1948-3287
3
0.69
References 
Authors
4
7
Name
Order
Citations
PageRank
Masaharu Terada182.25
Shusuke Yoshimoto23012.56
Shunsuke Okumura36312.54
Toshi-kazu Suzuki47311.00
Shinji Miyano58512.63
Hiroshi Kawaguchi639591.51
Masahiko Yoshimoto730.69