Shusuke Yoshimoto - Citegraph

Author Info

Name	Affiliation	Papers
SHUSUKE YOSHIMOTO	Kobe Univ, Grad Sch Syst Informat, Kobe, Hyogo 657, Japan	29
Collaborators	Citations	PageRank
81	30	12.56
Referers	Referees	References
123	305	91

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100305

Publications (29 rows)

Collaborators (81 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme	0	0.34	2019
Noise Evaluation System for Biosignal Sensors Using Pseudo-Skin and Helmholtz Coil	0	0.34	2019
Flexible Sensor Sheet For Real-Time Pressure Monitoring In Artificial Knee Joint During Total Knee Arthroplasty	0	0.34	2017
Wearable pulse wave velocity sensor using flexible piezoelectric film array.	0	0.34	2017
Flexible Organic Tft Bio-Signal Amplifier Using Reliable Chip Component Assembly Process With Conductive Adhesive	0	0.34	2017
A patch-type wireless forehead pulse oximeter for SpO2 measurement.	0	0.34	2017
Flexible Electronics For Bio-Signal Monitoring In Implantable Applications	0	0.34	2017
A 28-Nm 484-Fj/Writecycle 650-Fj/Readcycle 8t Three-Port Fd-Soi Sram For Image Processor	0	0.34	2016
Implantable wireless 64-channel system with flexible ECoG electrode and optogenetics probe.	0	0.34	2016
A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM.	0	0.34	2016
A negative-resistance sense amplifier for low-voltage operating STT-MRAM	2	0.37	2015
A Low Power 6t-4c Non-Volatile Memory Using Charge Sharing And Non-Precharge Techniques	0	0.34	2015
Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector	3	0.70	2015
A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems	3	0.60	2014
Soft-Error Resilient And Margin-Enhanced N-P Reversed 6t Sram Bitcell	0	0.34	2014
Stt-Mram Operating At 0.38 V Using Negative-Resistance Sense Amplifier	0	0.34	2014
Multiple-Cell-Upset Tolerant 6t Sram Using Nmos-Centered Cell Layout	0	0.34	2013
A 40-Nm 256-Kb Half-Select Resilient 8t Sram With Sequential Writing Technique	1	0.37	2012
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.	3	0.69	2012
A 128-Bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation In Sram Bitcells	0	0.34	2012
A 0.15-Mu M Fd-Soi Substrate Bias Control Sram With Inter-Die Variability Compensation Scheme	0	0.34	2012
A 40-Nm 0.5-V 12.9-Pj/Access 8t Sram Using Low-Energy Disturb Mitigation Scheme	1	0.39	2012
Neutron-induced soft error rate estimation for SRAM using PHITS	1	0.36	2012
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme	2	0.42	2012
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure	2	1.44	2012
Bit-Error And Soft-Error Resilient 7t/14t Sram With 150-Nm Fd-Soi Process	0	0.34	2012
A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10−19	5	0.50	2011
7t Sram Enabling Low-Energy Instantaneous Block Copy And Its Application To Transactional Memory	0	0.34	2011
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme	7	0.65	2009