Name
Abstract | ||
|---|---|---|
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalability, low cost, and energy efficiency. CGRAs have been effectively used for innermost loops that contain an abundant of instruction-level parallelism. Conversely, non-loop and outer-loop code are latency constrained and do not offer significant amounts of instruction-level parallelism. In these situations, CGRAs are ineffective as the majority of the resources remain idle. In this paper, dynamic operation fusion is introduced to enable CGRAs to effectively accelerate latency-constrained code regions. Dynamic operation fusion is enabled through the combination of a small bypass network added between function units in a conventional CGRA and a sub-cycle modulo scheduler to automatically identify opportunities for fusion. Results show that dynamic operation fusion reduced total application run-time by up to 17% on a 4x4 CGRA. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1145/1629395.1629433 | CASES |
Keywords | Field | DocType |
outer-loop code,high computation throughput,instruction-level parallelism,dynamic operation fusion,conventional cgra,appealing hardware platform,latency-constrained code region,coarse-grained reconfigurable architecture,function unit,energy efficiency,energy efficient,functional unit | Modulo,Computer science,Efficient energy use,Latency (engineering),Parallel computing,Fusion,Real-time computing,Throughput,Computation,Embedded system,Scalability | Conference |
Citations | PageRank | References |
33 | 1.07 | 20 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yongjun Park | 1 | 277 | 20.15 |
| Hyunchul Park | 2 | 341 | 17.56 |
| Scott Mahlke | 3 | 4811 | 312.08 |