Name
Abstract | ||
|---|---|---|
Silencer! is a new, fully automated, substrate noise coupling analysis tool that is integrated into the CADENCE DFII design environment. This tool seamlessly enables substrate noise coupling analysis in a standard mixed-signal design flow. IC designers can analyze substrate noise coupling at different levels of hierarchy - from the schematic level to the layout. Examples have been simulated and the results are accurate to within 10% of measured fabricated chips. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/SOCC.2004.1362367 | SoCC |
Keywords | Field | DocType |
circuit CAD,integrated circuit design,integrated circuit noise,mixed analogue-digital integrated circuits,substrates,CADENCE DFII design environment,IC design,Silencer!,mixed signal integrated circuits,mixed-signal design,substrate noise coupling analysis,system-on-chip | Silencer,Inductance,Coupling,Computer science,Schematic,Electronic engineering,Design flow,Integrated circuit design,Transistor,Integrated circuit | Conference |
ISSN | Citations | PageRank |
2164-1676 | 4 | 0.60 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Patrick Birrer | 1 | 14 | 2.33 |
| Terri S. Fiez | 2 | 167 | 47.25 |
| Kartikeya Mayaram | 3 | 349 | 58.50 |