A Highly Linear OTA-Less 1-1 MASH VCO-Based $\Delta\Sigma$ ADC With an Efficient Phase Quantization Noise Extraction Technique | 4 | 0.39 | 2020 |
0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique | 0 | 0.34 | 2019 |
A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4<sup>th</sup> order CT-ΔΣ modulator with 2<sup>nd</sup> order noise-shaping and pipelined SAR-VCO based quantizer | 0 | 0.34 | 2019 |
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation. | 4 | 0.52 | 2018 |
A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer | 0 | 0.34 | 2018 |
A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC. | 0 | 0.34 | 2017 |
A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation | 1 | 0.44 | 2017 |
Fast start-up analysis of resonator based oscillators using a power generation method. | 0 | 0.34 | 2016 |
A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator | 19 | 2.12 | 2015 |
12.9 A 1.55×0.85mm2 3ppm 1.0μA 32.768kHz MEMS-based oscillator | 0 | 0.34 | 2014 |
An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW. | 0 | 0.34 | 2013 |
A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks | 3 | 0.43 | 2013 |
A 12.5-bit 4 MHz 13.8 mW MASH $\Delta \Sigma$ Modulator With Multirated VCO-Based ADC | 9 | 0.75 | 2012 |
Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry | 2 | 0.39 | 2012 |
A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks | 0 | 0.34 | 2012 |
A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power. | 12 | 0.73 | 2012 |
A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC. | 0 | 0.34 | 2012 |
A Multiple-Input Boost Converter for Low-Power Energy Harvesting | 12 | 1.35 | 2011 |
A 250 Mv, 352 Mu W Gps Receiver Rf Front-End In 130 Nm Cmos | 15 | 1.30 | 2011 |
A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW. | 0 | 0.34 | 2011 |
A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency. | 13 | 1.01 | 2011 |
A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. | 8 | 0.85 | 2011 |
A 475 Mv, 4.9 Ghz Enhanced Swing Differential Colpitts Vco In 130 Nm Cmos With An Fom Of 196.2 Dbc/Hz | 4 | 0.60 | 2010 |
A Novel Low Power Hybrid Loop Filter For Continuous-Time Sigma-Delta Modulators | 1 | 0.59 | 2009 |
A Low Power Bfsk Super-Regenerative Transceiver | 2 | 0.54 | 2007 |
Tradeoffs In The Design Of Cmos Receivers For Low Power Wireless Sensor Networks | 1 | 0.37 | 2007 |
Simulation And Modeling Of Substrate Noise Generation From Synchronous And Asynchronous Digital Logic Circuits | 1 | 0.35 | 2007 |
A Green function-based parasitic extraction method for inhomogeneous substrate layers | 1 | 0.37 | 2005 |
Accurate prediction of substrate parasitics in heavily doped CMOS processes using a calibrated boundary element solver | 3 | 0.58 | 2005 |
Accurate and efficient simulation of synchronous digital switching noise in systems on a chip | 5 | 0.60 | 2005 |
A variable gain high linearity low power baseband filter for WLAN | 1 | 0.46 | 2004 |
An efficient formulation for substrate parasitic extraction accounting for nonuniform current distribution. | 2 | 0.41 | 2004 |
Silencer!: a tool for substrate noise coupling analysis. | 4 | 0.60 | 2004 |
An accurate and efficient estimation of switching noise in synchronous digital circuits | 1 | 0.39 | 2004 |
An improved Z-parameter macro model for substrate noise coupling | 0 | 0.34 | 2004 |
A Physical And Analytical Model For Substrate Noise Coupling Analysis | 1 | 0.73 | 2004 |
A Predictive Methodology For Accurate Substrate Parasitic Extraction | 0 | 0.34 | 2004 |
Strategies For Simulation, Measurement And Suppression Of Digital Noise In Mixed-Signal Circuits | 6 | 0.75 | 2003 |
Piezoelectric Power Generation Interface Circuits | 4 | 8.58 | 2003 |
Analysis of jitter in ring oscillators due to deterministic noise | 2 | 0.44 | 2002 |
Dynamic element matching in low oversampling delta sigma ADCs | 0 | 0.34 | 2002 |
Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer | 2 | 6.07 | 1999 |
Design-Oriented Substrate Noise Coupling Macromodels For Heavily Doped Cmos Processes | 2 | 0.46 | 1999 |
A low voltage CMOS current source | 2 | 0.51 | 1997 |
Improved Delta-Sigma DAC Linearity Using Data Weighted Averaging | 20 | 8.13 | 1995 |
Compact and Accurate MOST Model for Analog Circuit Hand Calculations | 0 | 0.34 | 1994 |
A 12 Bit, 2V Current-Mode Pipelined A/D Converter Nonlinearity | 0 | 0.34 | 1994 |
Asynchronous Implementation Of The Add Compare Select Processor For Communication Systems | 0 | 0.34 | 1994 |