Name
Affiliation
Papers
TERRI S. FIEZ
Oregon State University, Corvallis, OR
48
Collaborators
Citations 
PageRank 
88
167
47.25
Referers 
Referees 
References 
491
393
175
Search Limit
100491
Title
Citations
PageRank
Year
A Highly Linear OTA-Less 1-1 MASH VCO-Based $\Delta\Sigma$ ADC With an Efficient Phase Quantization Noise Extraction Technique40.392020
0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique00.342019
A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4<sup>th</sup> order CT-ΔΣ modulator with 2<sup>nd</sup> order noise-shaping and pipelined SAR-VCO based quantizer00.342019
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation.40.522018
A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer00.342018
A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC.00.342017
A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation10.442017
Fast start-up analysis of resonator based oscillators using a power generation method.00.342016
A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator192.122015
12.9 A 1.55×0.85mm2 3ppm 1.0μA 32.768kHz MEMS-based oscillator00.342014
An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW.00.342013
A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks30.432013
A 12.5-bit 4 MHz 13.8 mW MASH $\Delta \Sigma$ Modulator With Multirated VCO-Based ADC90.752012
Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry20.392012
A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks00.342012
A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power.120.732012
A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC.00.342012
A Multiple-Input Boost Converter for Low-Power Energy Harvesting121.352011
A 250 Mv, 352 Mu W Gps Receiver Rf Front-End In 130 Nm Cmos151.302011
A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW.00.342011
A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency.131.012011
A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer.80.852011
A 475 Mv, 4.9 Ghz Enhanced Swing Differential Colpitts Vco In 130 Nm Cmos With An Fom Of 196.2 Dbc/Hz40.602010
A Novel Low Power Hybrid Loop Filter For Continuous-Time Sigma-Delta Modulators10.592009
A Low Power Bfsk Super-Regenerative Transceiver20.542007
Tradeoffs In The Design Of Cmos Receivers For Low Power Wireless Sensor Networks10.372007
Simulation And Modeling Of Substrate Noise Generation From Synchronous And Asynchronous Digital Logic Circuits10.352007
A Green function-based parasitic extraction method for inhomogeneous substrate layers10.372005
Accurate prediction of substrate parasitics in heavily doped CMOS processes using a calibrated boundary element solver30.582005
Accurate and efficient simulation of synchronous digital switching noise in systems on a chip50.602005
A variable gain high linearity low power baseband filter for WLAN10.462004
An efficient formulation for substrate parasitic extraction accounting for nonuniform current distribution.20.412004
Silencer!: a tool for substrate noise coupling analysis.40.602004
An accurate and efficient estimation of switching noise in synchronous digital circuits10.392004
An improved Z-parameter macro model for substrate noise coupling00.342004
A Physical And Analytical Model For Substrate Noise Coupling Analysis10.732004
A Predictive Methodology For Accurate Substrate Parasitic Extraction00.342004
Strategies For Simulation, Measurement And Suppression Of Digital Noise In Mixed-Signal Circuits60.752003
Piezoelectric Power Generation Interface Circuits48.582003
Analysis of jitter in ring oscillators due to deterministic noise20.442002
Dynamic element matching in low oversampling delta sigma ADCs00.342002
Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer26.071999
Design-Oriented Substrate Noise Coupling Macromodels For Heavily Doped Cmos Processes20.461999
A low voltage CMOS current source20.511997
Improved Delta-Sigma DAC Linearity Using Data Weighted Averaging208.131995
Compact and Accurate MOST Model for Analog Circuit Hand Calculations00.341994
A 12 Bit, 2V Current-Mode Pipelined A/D Converter Nonlinearity00.341994
Asynchronous Implementation Of The Add Compare Select Processor For Communication Systems00.341994