Name
Abstract | ||
|---|---|---|
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to reduce both leakage as well as active power in a standard-cell library based high-performance design flow. We will discuss the design and cost issues for using different power saving techniques such as: power gating to reduce leakage, multiple and hybrid threshold libraries for leakage reduction and multiple supply voltage based design. In addition techniques to reduce clock tree power will be presented as power consumed in clocks accounts for a significant portion of total chip power. Practical aspects of implementing these techniques will also be discussed. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1145/1065579.1065653 | Design Automation Conference |
Keywords | Field | DocType |
design metrics,low power,clock tree power,leakage reduction,total chip power,vlsi design,hot chip,practical aspect,high-performance,multiple supply voltage,different power,active power,high-performance design flow,practical technique,low power electronics,chip,cmos integrated circuits,power dissipation,vlsi,cmos technology,frequency,design flow,threshold voltage,cmos,integrated circuit design | Leakage (electronics),Computer science,Design flow,CMOS,Electronic engineering,AC power,Chip,Integrated circuit design,Power gating,Low-power electronics | Conference |
ISSN | ISBN | Citations |
0738-100X | 1-59593-058-2 | 20 |
PageRank | References | Authors |
1.46 | 7 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ruchir Puri | 1 | 515 | 71.90 |
| Leon Stok | 2 | 179 | 18.69 |
| Subhrajit Bhattacharya | 3 | 462 | 36.93 |