Paper Info
Title
Design of a 3-D stacked floating-point adder.
Abstract
Three-dimensional (3-D) stacked integrated circuit (SIC) technologies have been expected to overcome the limitation in the design of microprocessors integrated by two-dimensional (2-D) implementations. 3-D SIC technologies enable to stack multiple integrated silicon layers. In the design of 3-D stacked arithmetic units, the circuits are partitioned into several sub-circuits, and each sub-circuit is placed on one layer. In order to exploit the potential of the 3-D SIC, a sophisticated partitioning should be required. In this paper, four partitioning patterns for a 3-D stacked floating-point adder are proposed, which are based on two basic ideas. One idea focuses on the structure of a 2-path floating point adder, and the other idea focuses on the large barrel shifters. Four implementations of a 3-D stacked double-precision floating-point adder are designed based on these partitioning patterns and evaluated. Experimental results show that the 3-D stacked double precision floating-point adder implemented on four layers achieves up to a 16.4% delay reduction compared to the 2-D implementation.
Year
DOI
Venue
2013
10.1109/3DIC.2013.6702390
3DIC
Keywords
Field
DocType
adders,delays,elemental semiconductors,floating point arithmetic,integrated circuit design,logic design,silicon,three-dimensional integrated circuits,2-path floating point adder,3D stacked arithmetic units,3D stacked double precision floating-point adder,3D stacked integrated circuits,delay reduction,integrated silicon layers,large barrel shifters,partitioning patterns
Logic synthesis,Adder,Floating point,Computer science,Double-precision floating-point format,Floating point adder,Integrated circuit design,Electronic circuit,Computer hardware,Integrated circuit
Conference
ISSN
Citations 
PageRank 
2164-0157
1
0.37
References 
Authors
5
3
Name
Order
Citations
PageRank
Jubee Tada174.69
Ryusuke Egawa210928.68
Hiroaki Kobayashi310814.52