Name
Abstract | ||
|---|---|---|
Soft errors, which have been a significant concern in memories, are now a main factor in reliability degradation of logic circuits. This paper presents a power-planning-aware methodology using dual supply voltages for soft error hardening. Given a constraint on power overhead, our proposed framework can minimize the soft error rate (SER) of a circuit via selective voltage assignment. In the 70-nm predictive technology model, circuit SER can be reduced by 23% on top of SER-aware gate resizing. For power-planning awareness, a bi-partitioning technique based on a simplified version of the Fiduccia–Mattheyses (FM) algorithm is presented. The simplified FM-based partitioning refines the result of selective voltage assignment by decreasing the number of connections across voltage islands, while maintaining the SER reduction that has been accomplished. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TVLSI.2012.2236658 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
selective voltage assignment,predictive technology model,logic circuits,integrated circuit reliability,power overhead,size 70 nm,power-planning-aware soft error hardening,fm algorithm,circuit ser minimization,power-planning-aware methodology,ser-aware gate resizing,dual-supply voltages,voltage assignment,fiduccia-mattheyses algorithm,logic circuit reliability degradation,partitioning,reliability,soft error rate (ser),voltage islands,simplified fm-based partitioning,bi-partitioning technique,soft errors,radiation hardening (electronics) | Logic gate,Soft error,Computer science,Voltage,Hardening (computing),Electronic engineering,Real-time computing,Voltage islands,Electrical engineering | Journal |
Volume | Issue | ISSN |
22 | 1 | 1063-8210 |
Citations | PageRank | References |
3 | 0.38 | 0 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kai-Chiang Wu | 1 | 113 | 13.98 |
| Diana Marculescu | 2 | 2725 | 223.87 |