Kai-Chiang Wu - Citegraph

Author Info

Name	Affiliation	Papers
KAI-CHIANG WU	National Tsing Hua University, Hsinchu, Taiwan	28
Collaborators	Citations	PageRank
55	113	13.98
Referers	Referees	References
287	371	205

Search Limit

100371

Publications (28 rows)

Collaborators (55 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
An Energy-Efficient Approximate Systolic Array Based on Timing Error Prediction and Prevention	0	0.34	2021
Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks	0	0.34	2021
CNN-based Stochastic Regression for IDDQ Outlier Identification	1	0.35	2020
Making Aging Useful by Recycling Aging-induced Clock Skew	0	0.34	2020
Selective Sensor Placement for Cost-Effective Online Aging Monitoring and Resilience	0	0.34	2020
Test Methodology for Defect-based Bridge Faults	0	0.34	2020
Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator	0	0.34	2020
Sensor-Based Approximate Adder Design For Accelerating Error-Tolerant And Deep-Learning Applications	0	0.34	2019
Layout-Based Dual-Cell-Aware Tests	0	0.34	2019
Methodology of Generating Timing-Slack-Based Cell-Aware Tests	1	0.37	2019
Aging-aware chip health prediction adopting an innovative monitoring strategy.	0	0.34	2019
Sensor-Based Time Speculation in the Presence of Timing Variability.	0	0.34	2018
MAUI: Making aging useful, intentionally	0	0.34	2018
Lifetime Reliability Trojan Based on Exploring Malicious Aging	0	0.34	2018
Analysis and optimization of variable-latency designs in the presence of timing variability.	0	0.34	2017
Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment	3	0.38	2014
A low-cost, systematic methodology for soft error robustness of logic circuits	15	1.34	2013
Mitigating lifetime underestimation: a system-level approach considering temperature variations and correlations between failure mechanisms	3	0.50	2012
Aging-aware timing analysis and optimization considering path sensitization	11	0.60	2011
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits	7	0.48	2011
Clock skew scheduling for soft-error-tolerant sequential circuits	2	0.36	2010
Joint logic restructuring and pin reordering against NBTI-induced performance degradation	28	1.07	2009
Process variability-aware transient fault modeling and analysis	4	0.44	2008
Soft error rate reduction using redundancy addition and removal	13	0.84	2008
Power-aware soft error hardening via selective voltage scaling	0	0.34	2008
Contouring Control of Smooth Paths for Multiaxis Motion Systems Based on Equivalent Errors	22	1.76	2007
Delay variation tolerance for domino circuits	0	0.34	2006
Re-synthesis for delay variation tolerance	3	0.41	2004