Paper Info
Title
Hardware Accelerated Data Analysis
Abstract
In this paper we present a massively parallel hardware accelerator for neural network based data mining applications. We use Self-Organizing Maps (SOM) for the analysis of very large datasets. One example is the analysis of semiconductor fabrication process data, which demands very high performance in order to achieve acceptable simulation times. Our system consists of Processing Elements (PEs) working completely in parallel on the task of SOM simulation. We will show the scalability of the system concerning precision and number of PEs, as well as the flexibility of the system regarding size and shape of the simulated maps. The possibility of emulating virtual maps (one PE emulates more than one neuron) enables the computation of maps with more neurons than PEs. Benchmarking results of our FPGA (Field Programmable Gate Array) based implementation of the system show the high performance of our accelerator.
Year
DOI
Venue
2004
10.1109/PARELEC.2004.36
PARELEC
Keywords
Field
DocType
parallel hardware accelerator,semiconductor fabrication process data,hardware accelerated data analysis,acceptable simulation time,large datasets,high performance,processing elements,som simulation,field programmable gate array,benchmarking result,data mining application,data analysis,neural networks,statistical analysis,fpga,neural network,statistics,acceleration,data mining,hardware accelerator,parallel processing,self organizing maps,integrated circuit layout,field programmable gate arrays,computational modeling
Integrated circuit layout,Computer science,Massively parallel,Semiconductor device fabrication,Parallel computing,Field-programmable gate array,Self-organizing map,Hardware acceleration,Computer hardware,Artificial neural network,Scalability
Conference
ISBN
Citations 
PageRank 
0-7695-2080-4
4
0.78
References 
Authors
4
4
Name
Order
Citations
PageRank
Marc Franzmeier1182.56
Christopher Pohl2394.91
Mario Porrmann342050.91
Ulrich Ruckert4717.70