| Numerical and Experimental Evaluation of Error Estimation for Two-Way Ranging Methods. | 4 | 0.51 | 2019 |
| FPGA-Based Vision Processing System for Automatic Online Player Tracking in Indoor Sports | 0 | 0.34 | 2019 |
| CoreVA-MPSoC: A Many-Core Architecture with Tightly Coupled Shared and Local Data Memories. | 2 | 0.39 | 2018 |
| Development of Energy Models for Design Space Exploration of Embedded Many-Core Systems. | 0 | 0.34 | 2018 |
| An Analytical Study of Time of Flight Error Estimation in Two-Way Ranging Methods | 2 | 0.40 | 2018 |
| LEGaTO: towards energy-efficient, secure, fault-tolerant toolset for heterogeneous computing | 4 | 0.38 | 2018 |
| OLT(RE): An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems. | 0 | 0.34 | 2018 |
| FPGA-based multi-robot tracking. | 0 | 0.34 | 2017 |
| M2DC - Modular Microserver DataCentre with heterogeneous hardware. | 2 | 0.43 | 2017 |
| Comparing Synchronous, Mesochronous and Asynchronous NoCs for GALS Based MPSoCs | 0 | 0.34 | 2017 |
| The M2DC Project: Modular Microserver DataCentre. | 2 | 0.39 | 2016 |
| Data centres for IoT applications: The M2DC approach (Invited paper) | 0 | 0.34 | 2016 |
| Performance Estimation Of Streaming Applications For Hierarchical Mpsocs | 0 | 0.34 | 2016 |
| Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI | 4 | 0.44 | 2015 |
| Evaluation Of Interconnect Fabrics For An Embedded Mpsoc In 28 Nm Fd-Soi | 2 | 0.40 | 2015 |
| A 65 nm standard cell library for ultra low-power applications | 1 | 0.41 | 2015 |
| System-Level Analysis of Network Interfaces for Hierarchical MPSoCs | 2 | 0.39 | 2015 |
| On-line testing of permanent radiation effects in reconfigurable systems | 4 | 0.48 | 2013 |
| A systematic approach for optimized bypass configurations for application-specific embedded processors | 1 | 0.38 | 2013 |
| A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control | 6 | 0.60 | 2013 |
| Mini-Robot's Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling | 0 | 0.34 | 2012 |
| gNBXe - a Reconfigurable Neuroprocessor for Various Types of Self-Organizing Maps. | 0 | 0.34 | 2012 |
| A TCMS-based architecture for GALS NoCs | 5 | 0.50 | 2012 |
| A 200mV 32b subthreshold processor with adaptive supply voltage control. | 0 | 0.34 | 2012 |
| Evaluation of Applied Intra-disk Redundancy Schemes to Improve Single Disk Reliability | 8 | 0.46 | 2011 |
| Applying dynamic reconfiguration in the mobile robotics domain: A case study on computer vision algorithms | 10 | 0.60 | 2011 |
| Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs | 11 | 0.95 | 2011 |
| A Framework for the Design Space Exploration of Software-Defined Radio Applications | 2 | 0.41 | 2010 |
| Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis | 0 | 0.34 | 2010 |
| Design Space Exploration for Memory Subsystems of VLIW Architectures | 4 | 0.49 | 2010 |
| A Synchronization Method for Register Traces of Pipelined Processors | 3 | 0.46 | 2009 |
| Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing | 1 | 0.39 | 2009 |
| Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance | 5 | 0.48 | 2009 |
| SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems | 3 | 0.60 | 2009 |
| RAPTOR A Scalable Platform for Rapid Prototyping and FPGA-based Cluster Computing. | 13 | 0.97 | 2009 |
| vMAGIC-Automatic Code Generation for VHDL | 11 | 0.96 | 2009 |
| Design optimizations to improve placeability of partial reconfiguration modules | 6 | 0.50 | 2009 |
| Run-time reconfigurability in embedded multiprocessors | 0 | 0.34 | 2009 |
| SelfS - A real-time protocol for virtual ring topologies | 1 | 0.37 | 2008 |
| Resource Efficiency of Instruction Set Extensions for Elliptic Curve Cryptography | 0 | 0.34 | 2008 |
| A multiprocessor cache for massively parallel soc architectures | 1 | 0.43 | 2007 |
| Resource efficiency of the GigaNetIC chip multiprocessor architecture | 7 | 0.63 | 2007 |
| GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors | 13 | 0.82 | 2007 |
| Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs | 20 | 1.64 | 2007 |
| Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux | 13 | 1.32 | 2007 |
| A Design Framework For Fpga-Based Dynamically Reconfigurable Digital Controllers | 3 | 0.40 | 2007 |
| GigaNetIC – a scalable embedded on-chip multiprocessor architecture for network applications | 3 | 0.48 | 2006 |
| Relocation and Defragmentation for Heterogeneous Reconfigurable Systems | 4 | 0.55 | 2006 |
| REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs | 43 | 2.38 | 2006 |
| Bio-inspired massively parallel architectures for nanotechnologies | 0 | 0.34 | 2006 |
