Name
Abstract | ||
|---|---|---|
In this paper, test time reduction for I DDQ testing isdiscussed. Although I DDQ testing is known to be effectiveto detect faults in CMOS circuit, test time of IDDQ testingis larger than that of logic testing. It is shown that testtime of I DDQ test mostly depends on switching current. Toreduce test time of I DDQ testing, the procedure to arrangetest vectors such that switching current quickly disappearsis proposed for combinational circuits. The procedureutilizes a unit delay model to estimate the time of the lasttransition of logic value from L to H in a circuit.Experimental results for benchmark circuits show theeffectiveness of the procedure. |
Year | Venue | Keywords |
|---|---|---|
2002 | Asian Test Symposium | Test Time Reduction,Arranging Test Vectors,benchmark circuit,test time reduction,test time,logic value,logic testing,CMOS circuit,I DDQ Testing,DDQ testing,experimental result,combinational circuit,Toreduce test time |
Field | DocType | ISBN |
Automatic test pattern generation,Digital electronics,Sequential logic,Pass transistor logic,Logic optimization,Computer science,Algorithm,Electronic engineering,Real-time computing,Combinational logic,Logic family,Integrated injection logic | Conference | 0-7695-1825-7 |
Citations | PageRank | References |
1 | 0.36 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroyuki Yotsuyanagi | 1 | 70 | 19.04 |
| Masaki Hashizume | 2 | 98 | 27.83 |
| Takeomi Tamesada | 3 | 45 | 12.49 |