Hiroyuki Yotsuyanagi

Author Info

Name	Affiliation	Papers
HIROYUKI YOTSUYANAGI	Univ Tokushima, Dept Informat Solut, Inst Sci & Technol, 2-1 Minami Josanjima, Tokushima 7708506, Japan	46
Collaborators	Citations	PageRank
61	70	19.04
Referers	Referees	References
154	455	296

Search Limit

100455

Publications (46 rows)

Collaborators (61 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Fault-Aware Dependability Enhancement Techniques for Flash Memories	0	0.34	2020
On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC	0	0.34	2019
A Design For Testability Of Open Defects At Interconnects In 3d Stacked Ics	0	0.34	2018
A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification	0	0.34	2018
Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design	0	0.34	2018
On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects	0	0.34	2017
Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs	0	0.34	2017
Discrimination Of A Resistive Open Using Anomaly Detection Of Delay Variation Induced By Transitions On Adjacent Lines	0	0.34	2017
A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume	0	0.34	2017
Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories	0	0.34	2017
On TSV array defect detection method using two ring-oscillators considering signal transitions at adjacent TSVs	0	0.34	2015
On Detecting Delay Faults Using Time-To-Digital Converter Embedded In Boundary Scan	2	0.41	2013
Sat-Based Test Generation For Open Faults Using Fault Excitation Caused By Effect Of Adjacent Lines	1	0.37	2013
Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture	5	0.48	2011
A built-in test circuit for open defects at interconnects between dies in 3D ICs.	0	0.34	2011
Scan Chain Ordering To Reduce Test Data For Bist-Aided Scan Test Using Compatible Scan Flip-Flops	1	0.36	2010
Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code	0	0.34	2010
New Class of Tests for Open Faults with Considering Adjacent Lines	2	0.38	2009
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC	5	0.50	2009
A Novel Approach for Improving the Quality of Open Fault Diagnosis	5	0.49	2009
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines	5	0.49	2007
Current Testable Design of Resistor String DACs	1	0.38	2006
Reducing scan shifts using configurations of compatible and folding scan trees	4	0.45	2005
Electric field for detecting open leads in CMOS logic circuits by supply current testing	0	0.34	2005
Identification And Frequency Estimation Of Feedback Bridging Faults Generating Logical Oscillation In Cmos Circuits	0	0.34	2004
CMOS Open Fault Detection by Appearance Time of Switching Supply Current	1	0.44	2004
A test circuit for pin shorts generating oscillation in CMOS logic circuits	1	0.36	2004
Practical Fault Coverage of Supply Current Tests for Bipolar ICs	0	0.34	2004
Test Sequence Generation For Test Time Reduction Of Iddq Testing	0	0.34	2004
A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits	1	0.35	2004
I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment	0	0.34	2004
Reducing Scan Shifts Using Folding Scan Trees	12	0.87	2003
A BIST Circuit for IDDQ Tests	1	0.36	2003
Test Time Reduction for I DDQ Testing by Arranging Test Vectors	1	0.36	2002
Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits	3	0.65	2002
Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field	0	0.34	2002
Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field	2	0.56	2001
IDDQ sensing technique for high speed IDDQ testing	0	0.34	2001
Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States	0	0.34	2001
CMOS open defect detection based on supply current in time-variable electric field and supply voltage application	1	0.43	2001
Testability analysis of IDDQ testing with large threshold value	0	0.34	2000
Identification of feedback bridging faults with oscillation	6	0.56	1999
Undetectable fault removal of sequential circuits based on unreachable states	6	1.00	1998
Synthesis of Sequential Circuits by Redundancy Removal and Retiming	2	0.54	1997
Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement.	0	0.34	1995
Synthesis for Testability by Sequential Redundancy Removal Using Retiming	2	0.46	1995