Name
Abstract | ||
|---|---|---|
In a system-on-a-chip (SOC) design, several to hundreds of design blocks or intellectual properties (IPs) are integrated to form a complex function. Prior to verify the functionality of the integrated IPs, it is very important to ensure the correctness of the port connections among these IPs. This paper addresses the problem of verification on port connections while IPs are integrated into a larger block or a system, and presents a new connection model and the corresponding error model for port connections. An algorithm providing the minimum pattern set and a general verification flow used to verify port connections are also proposed. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ITC.2004.200 | ITC |
Keywords | Field | DocType |
larger block,new connection model,general verification flow,intellectual property,complex function,port connection,design block,integrated ips,minimum pattern set,corresponding error model,port connections,integrated circuit design,system on chip,system on a chip | System on a chip,Computer science,Correctness,Computer Aided Design,Printed circuit board,Electronic engineering,Integrated circuit design,Mathematical model,Integrated circuit | Conference |
ISBN | Citations | PageRank |
0-7803-8581-0 | 0 | 0.34 |
References | Authors | |
9 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Geeng-Wei Lee | 1 | 14 | 2.21 |
| Juinn-Dar Huang | 2 | 270 | 27.42 |
| Jing-Yang Jou | 3 | 681 | 88.55 |
| Wang Chun-Yao | 4 | 251 | 36.08 |