| Hardware-Friendly Progressive Pruning Framework for CNN Model Compression using Universal Pattern Sets | 0 | 0.34 | 2022 |
| Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy | 0 | 0.34 | 2022 |
| Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model | 0 | 0.34 | 2021 |
| High-Speed Power-Efficient Coarse-Grained Convolver Architecture using Depth-First Compression Scheme | 0 | 0.34 | 2020 |
| A Coarse-Grained Dual-Convolver Based CNN Accelerator with High Computing Resource Utilization | 0 | 0.34 | 2020 |
| Storage-Aware Algorithms for Dilution and Mixture Preparation With Flow-Based Lab-on-Chip. | 1 | 0.35 | 2020 |
| Forecast-Based Sample Preparation Algorithm for Unbalanced Splitting Correction on DMFBs | 0 | 0.34 | 2019 |
| A Comprehensive Security System for Digital Microfluidic Biochips | 1 | 0.35 | 2018 |
| Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays | 0 | 0.34 | 2018 |
| Dilution and Mixing Algorithms for Flow-Based Microfluidic Biochips. | 11 | 0.60 | 2017 |
| Volume-oriented sample preparation for reactant minimization on flow-based microfluidic biochips with multi-segment mixers | 8 | 0.50 | 2015 |
| Probability-Based Static Scaling Optimization for Fixed Wordlength FFT Processors. | 0 | 0.34 | 2014 |
| Ilp-Based Bitwidth-Aware Subexpression Sharing For Area Minimization In Multiple Constant Multiplication | 0 | 0.34 | 2014 |
| Two-staged parallel layer-aware partitioning for 3D designs | 0 | 0.34 | 2014 |
| Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints | 7 | 0.62 | 2014 |
| Sample preparation for droplet-based microfluidics | 0 | 0.34 | 2014 |
| Reactant and Waste Minimization in Multitarget Sample Preparation on Digital Microfluidic Biochips | 22 | 0.92 | 2013 |
| Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing | 17 | 0.69 | 2013 |
| Latency-optimization synthesis with module selection for digital microfluidic biochips | 6 | 0.41 | 2013 |
| Tutorial: Digital Microfluidic Biochips: Towards Hardware/Software Co-Design And Cyber-Physical System Integration | 0 | 0.34 | 2013 |
| Graph-based optimal reactant minimization for sample preparation on digital microfluidic biochips | 20 | 0.93 | 2013 |
| Performance-driven architectural synthesis for distributed register-file microarchitecture considering inter-island delay | 3 | 0.43 | 2012 |
| Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing trees | 43 | 1.84 | 2012 |
| Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only) | 0 | 0.34 | 2012 |
| Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. | 0 | 0.34 | 2012 |
| Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family | 0 | 0.34 | 2011 |
| Equivalence checking of scheduling with speculative code transformations in high-level synthesis | 17 | 0.82 | 2011 |
| Throughput optimization for latency-insensitive system with minimal queue insertion | 2 | 0.37 | 2011 |
| Layer-Aware Design Partitioning for Vertical Interconnect Minimization | 5 | 0.42 | 2011 |
| Communication Synthesis For Interconnect Minimization Targeting Distributed Register-File Microarchitecture | 2 | 0.40 | 2011 |
| Expandable MDC-based FFT architecture and its generator for high-performance applications. | 0 | 0.34 | 2010 |
| FSM-Based Formal Compliance Verification of Interface Protocols | 0 | 0.34 | 2010 |
| A Hierarchical Criticality-Aware Architectural Synthesis Framework For Multicycle Communication | 4 | 0.45 | 2010 |
| Automatic verification stimulus generation for interface protocols modeled with non-deterministic extended FSM | 1 | 0.43 | 2009 |
| Communication Synthesis For Interconnect Minimization In Multicycle Communication Architecture | 3 | 0.39 | 2009 |
| CriAS: A performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture | 4 | 0.41 | 2009 |
| Reducing fault dictionary size for million-gate large circuits | 1 | 0.36 | 2009 |
| Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture | 3 | 0.40 | 2009 |
| Low power multiplexer tree design using dynamic propagation path control | 0 | 0.34 | 2008 |
| A multicycle communication architecture and synthesis flow for global interconnect resource sharing | 5 | 0.47 | 2008 |
| Cycle-time-aware sequential way-access set-associative cache for low energy consumption | 0 | 0.34 | 2008 |
| Verification of Pin-Accurate Port Connections | 0 | 0.34 | 2008 |
| Fault Dictionary Size Reduction for Million-Gate Large Circuits | 3 | 0.44 | 2007 |
| A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses | 4 | 0.46 | 2007 |
| FSM-based transaction-level functional coverage for interface compliance verification | 3 | 0.41 | 2006 |
| A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication | 8 | 0.69 | 2006 |
| Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model | 8 | 0.52 | 2005 |
| Verification on Port Connections | 0 | 0.34 | 2004 |
| Unified functional decomposition via encoding for FPGA technology mapping | 2 | 0.45 | 2001 |
| ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping | 2 | 0.41 | 2000 |
