Name
Abstract | ||
|---|---|---|
Networks-on-Chip (NoCs) are scalable fabrics for interconnection networks used in many-core architectures. ORION2.0 is a widely adopted NoC power and area estimation tool; however, its models for area, power and gate count can have large errors (up to 110% on average) versus actual implementation. In this work, we propose a new methodology that analyzes netlists of NoC routers that have been placed and routed by commercial tools, and then performs explicit modeling of control and data paths followed by regression analysis to create highly accurate gate count, area and power models for NoCs. When compared with actual implementations, our new models have average estimation errors of no more than 9.8% across microarchitecture and implementation parameters. We further describe modeling extensions that enable more detailed flit-level power estimation when integrated with simulation tools such as GARNET. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1145/2228360.2228430 | DAC |
Keywords | Field | DocType |
integrated circuit interconnections,multiprocessing systems,network routing,network-on-chip,regression analysis,GARNET,NoC area estimation tool,NoC power estimation tool,ORION2.0,area model,explicit control modeling,explicit data modeling,flit-level power estimation,gate count,improved NoC router estimation,interconnection networks,many-core architectures,networks-on-chip,power model,regression analysis,flit-level power modeling,network-on-chip,parametric regression | Data modeling,Gate count,Computer science,Network on a chip,Electronic engineering,Real-time computing,Router,Interconnection,AND gate,Microarchitecture,Scalability | Conference |
ISSN | Citations | PageRank |
0738-100X | 30 | 1.35 |
References | Authors | |
16 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andrew B. Kahng | 1 | 7582 | 859.06 |
| B. Lin | 2 | 1405 | 126.39 |
| Siddhartha Nath | 3 | 240 | 15.01 |