Name
Abstract | ||
|---|---|---|
The difference-bit cache is a two-way set-associative cache with an access time that is smaller than that of a conventional one and close or equal to that of a direct-mapped cache. This is achieved by noticing that the two tags for a set have to differ at least by one bit and by using this bit to select the way. In contrast with previous approaches that predict the way and have two types of hits (primary of one cycle and secondary of two to four cycles), all hits of the difference-bit cache are of one cycle. The evaluation of the access time of our cache organization has been performed using a recently proposed on-chip cache access model.
|
Year | DOI | Venue |
|---|---|---|
1996 | 10.1145/232974.232986 | Special Interest Group on Computer Architecture |
Keywords | Field | DocType |
correlation,computer architecture,chip,branch prediction | Cache invalidation,Cache pollution,Computer science,Cache,Snoopy cache,Parallel computing,Cache algorithms,Page cache,Real-time computing,Cache coloring,Smart Cache | Conference |
Volume | Issue | ISSN |
24 | 2 | 0163-5964 |
ISBN | Citations | PageRank |
0-89791-786-3 | 17 | 1.28 |
References | Authors | |
14 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Toni Juan | 1 | 520 | 41.42 |
| Tomás Lang | 2 | 17 | 1.28 |
| Juan J. Navarro | 3 | 323 | 42.90 |