Paper Info
Title
The M-Machine multicomputer
Abstract
The M-Machine is an experimental multicomputer being developed to test architectural concepts motivated by the constraints of modern semiconductor technology and the demands of programming systems. The M-Machine computing nodes are connected with a 3-D mesh network; each node is a multithreaded processor incorporating 9 function units, on-chip cache, and local memory. The multiple function units are used to exploit both instruction-level and thread-level parallelism. A user accessible message passing system yields fast communication and synchronization between nodes. Rapid access to remote memory is provided transparently to the user with a combination of hardware and software mechanisms. This paper presents the architecture of the M-Machine and describes how its mechanisms attempt to maximize both single thread performance and overall system throughput. The architecture is complete and the MAP chip, which will serve as the M-Machine processing node, is currently being implemented.
Year
DOI
Venue
1997
10.1007/BF02700035
MICRO95: 28th Annual IEEE/ACM International Symposium on Microarchitecture Ann Arbor Michigan USA November, 1995
Keywords
Field
DocType
multithreading,m-machine multicomputer,computer architecture,coherence.,parallelism,thread level parallelism,coherence,mesh network,functional unit,chip
Mesh networking,Multithreading,Synchronization,CPU cache,Computer science,Cache,Parallel computing,Thread (computing),Systems architecture,Throughput,Embedded system
Journal
Volume
Issue
ISSN
25
3
0885-7458
ISBN
Citations 
PageRank 
0-8186-7349-4
85
14.67
References 
Authors
16
7
Name
Order
Citations
PageRank
Marco Fillo110618.80
Stephen W. Keckler23404201.71
William J. Dally3117821460.14
Nicholas P. Carter434933.84
Andrew Chang58514.67
Yevgeny Gurevich68514.67
Whay Sing Lee79915.98