Name
Abstract | ||
|---|---|---|
Three-Dimensional (3D) Integrated Circuits (ICs) that integrate die with Through-Silicon Vias (TSVs) promise to continue system and functionality scaling beyond the traditional geometric 2D device scaling. 3D integration also improves the performance of ICs by reducing the communication time between different chip components through the use of short TSV-based vertical wires. This reduction is particularly attractive in processors where it is desirable to reduce the access time between the main logic die and the L2 cache or the main memory die. Process variations in 2D ICs lead to a drop in parametric yield (as measured by speed, leakage and sales profits), which forces manufacturers to speed bin their chips and to sell slow chips at reduced prices. In this paper we develop a model to quantify the impact of process variations on the parametric yield of 3D ICs, and then we propose a number of integration strategies that use a graph-theoretic framework to maximize the performance, parametric yield and profits of 3D ICs. Comparing our proposed strategies to current yield-oblivious methods, it is demonstrated that it is possible to increase the number of 3D ICs in the fastest speed bins by almost 2×, while simultaneously reducing the number of slow ICs by 29.4%. This leads to an improvement in performance by up to 6.45% and an increase of about 12.48% in total sales revenue using up-to-date market price models. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1412587.1412592 | JETC |
Keywords | Field | DocType |
access time,additional key words and phrases: 3d integration,leakage,process variations,process variation,fastest speed bin,functionality scaling,main logic die,parametric yield,communication time,yield management acm reference format:,parametric yield management,performance,device scaling,slow ics,integration strategy,chip,three dimensional,profitability,through silicon via,yield management | Access time,Leakage (electronics),Bin,CPU cache,Computer science,Yield management,Electronic engineering,Chip,Parametric statistics,Integrated circuit | Journal |
Volume | Issue | ISSN |
4 | 4 | 1550-4832 |
Citations | PageRank | References |
24 | 1.66 | 28 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cesare Ferri | 1 | 115 | 6.78 |
| Sherief Reda | 2 | 1283 | 92.25 |
| R. Iris Bahar | 3 | 878 | 84.31 |